Steady state noise modeling in computer chips using neural networks

  • Authors:

  • Vaibhav Nawale;Tom Chen

  • Affiliations:

  • Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, CO;Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, CO

  • Venue:
  • AIAP'07 Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: artificial intelligence and applications
  • Year:
  • 2007

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Abstract

With continuing growth of computer technology, computer CPU chips are following the Moore's Law for decades, resulting in ever smaller geometry (currently at 65nm), and ever increasing complexity. One of the major issues in designing computer chips is to estimate the steady state noise between driving sources. Excessive noise level at a given node in a circuit can cause logic failures. The conventional method to obtain the steady state noise level is through table lookup where a large amount of lookup tables are generated. This method is simple but is tedious and requires a large amount of storage space. This paper proposes a new method of using neural networks to model the steady state noise level. The proposed method provides a simple and accurate method to determine steady state noise, and yet requires much less storage space.