Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Computer
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
UniTesK Test Suite Architecture
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
The UniTESK Approach to Specification-Based Validation of Hardware Designs
ISOLA '06 Proceedings of the Second International Symposium on Leveraging Applications of Formal Methods, Verification and Validation
Model-based testing of internet e-mail protocols
Programming and Computing Software
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Contract specifications in the form of pre-and postconditions are widely used in software engineering for formal description of interfaces of software components. On the one hand, such specifications are convenient for the developers since they can easily be attached to the system architecture. On the other hand, test oracles verifying conformance of the behavior of the target system to the specifications can automatically be generated from them. In the paper, it is suggested to use contract specifications for representing requirements and for functional testing of hardware models developed in languages such as VHDL, Verilog, SystemC, System Verilog, etc. An approach to specification of such systems is proposed and compared with the existing methods of hardware specification. An experience of its practical use is described. The approach is based on the UniTESK testing technology developed at the Institute for System Programming.