RF microelectronics
Fast settling PLL frequency synthesizer utilizing the frequency detector method speedup circuit
IEEE Transactions on Consumer Electronics
Analysis and minimization of phase noise of the digital hybrid PLL frequency synthesizer
IEEE Transactions on Consumer Electronics
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This paper presents an exact method for the loop parameters' calculation. The noise transfer functions of PLL based synthesizers are derived in the z-domain analysis. Through the comparison of the s-domain model with the z-domain model, we show that the noise peak from inherent sampling behaviors always exists in the loop, and the loop filter with the wide loop bandwidth doesn't suppress it. Such a noise peak causes instability to the system. A stability limit of the wide loop bandwidth frequency synthesizer is extracted by the behavioral simulation using the z-domain model, which depends on the phase margin and the ratio between the reference frequency and the loop bandwidth.