A Novel (N + 1/2) Pulse Swallow Programmable Divider for the Prescaler PLL Frequency Synthesizer
Analog Integrated Circuits and Signal Processing - Selected papers from the 1st Analog VLSI Workshop
Noise transfer characteristics and design techniques of a frequency synthesizer
Analog Integrated Circuits and Signal Processing
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We propose two items for the fast frequency settling in the phase locked loop (PLL) frequency synthesizer. One is a PLL frequency synthesizer utilizing a frequency detector method speedup circuit (FDMSC). From the experimental results, it is observed that fast frequency settling can be achieved. The other is a shortcut lowpass filter (LPF) method with the FDMSC in the PLL frequency synthesizer. The frequency settling time has been speeded up further by changing the time constant of the LPF to a smaller value only in the rising condition