Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
ESoftCheck: Removal of Non-vital Checks for Fault Tolerance
Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization
End-to-end register data-flow continuous self-test
Proceedings of the 36th annual international symposium on Computer architecture
An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2
Proceedings of the ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2
ACM SIGMETRICS Performance Evaluation Review - Performance evaluation review
A survey of checker architectures
ACM Computing Surveys (CSUR)
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A significant fraction of the circuitry in a modern processor is dedicated to converting the linear instruction stream into a representation that allows the execution of instructions in data dependence order, rather than program order, to extract instruction level parallelism. All errors caused by hardware faults in this circuitry-- which includes the fetch and decode stages, renaming and scheduling logic, as well as the commit stage--will manifest themselves as incorrectly constructed dataflow graphs. Dynamic Dataflow Verification (DDFV) compares the dynamically constructed and executed dataflow graph to the expected dataflow graph of the static program binary, represented by a signature embedded in the instruction stream. The signature comparison enables comprehensive detection of transient errors, permanent errors, and design bugs in the dataflow circuitry. We show that DDFV detects errors with high probability, at a low hardware and performance cost.