A survey of checker architectures

  • Authors:

  • Rajshekar Kalayappan;Smruti R. Sarangi

  • Affiliations:

  • Indian Institute of Technology, New Delhi, India;Indian Institute of Technology, New Delhi, India

  • Venue:
  • ACM Computing Surveys (CSUR)
  • Year:
  • 2013

Quantified Score

Hi-index 0.00

Visualization

Abstract

Reliability is quickly becoming a primary design constraint for high-end processors because of the inherent limits of manufacturability, extreme miniaturization of transistors, and the growing complexity of large multicore chips. To achieve a high degree of fault tolerance, we need to detect faults quickly and try to rectify them. In this article, we focus on the former aspect. We present a survey of different kinds of fault detection mechanisms for processors at circuit, architecture, and software level. We collectively refer to such mechanisms as checker architectures. First, we propose a novel two-level taxonomy for different classes of checkers based on their structure and functionality. Subsequently, for each class we present the ideas in some of the seminal papers that have defined the direction of the area along with important extensions published in later work.