Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features
Journal of Electronic Testing: Theory and Applications
A New Hybrid Fault Detection Technique for Systems-on-a-Chip
IEEE Transactions on Computers
Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
An optimized hybrid approach to provide fault detection and correction in SoCs
Proceedings of the 20th annual conference on Integrated circuits and systems design
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
Journal of Electronic Testing: Theory and Applications
Error Detection Enhancement in PowerPC Architecture-based Embedded Processors
Journal of Electronic Testing: Theory and Applications
Concepts for Autonomous Control Flow Checking for Embedded CPUs
ATC '08 Proceedings of the 5th international conference on Autonomic and Trusted Computing
Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs
International Journal of Autonomous and Adaptive Communications Systems
mSWAT: low-cost hardware fault detection and diagnosis for multicore systems
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
On-line control flow error detection using relationship signatures among basic blocks
Computers and Electrical Engineering
A rapid prototyping system for error-resilient multi-processor systems-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Design techniques for cross-layer resilience
Proceedings of the Conference on Design, Automation and Test in Europe
A hybrid hardware--software technique to improve reliability in embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
Exploring the Limitations of Software-based Techniques in SEE Fault Coverage
Journal of Electronic Testing: Theory and Applications
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Time-Constraint-Aware Optimization of Assertions in Embedded Software
Journal of Electronic Testing: Theory and Applications
Evaluation and analysis of an on-line error detection monitoring technique
Computers and Electrical Engineering
Low cost control flow protection using abstract control signatures
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
A survey of checker architectures
ACM Computing Surveys (CSUR)
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Over the last years, an increasing number of safety-critical tasks have been demanded tocomputer systems. In this paper, a software-based approach for developing safety-criticalapplications is analyzed. The technique is based on the introduction of additional executableassertions to check the correct execution of the program control flow. By applying the proposed technique, several benchmark applications have been hardened against transienterrors. Fault Injection campaigns have been performed to evaluate the fault detection capability of the proposed technique in comparison with state-of-the-art alternative assertion-based methods. Experimental results show that the proposed approach is far more effective than the other considered techniques in terms of fault detection capability, at the cost of a limited increase in memory requirements and in performance overhead.