Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Processor Control Flow Monitoring Using Signatured Instruction Streams
IEEE Transactions on Computers
Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection
IEEE Transactions on Parallel and Distributed Systems
ED4I: Error Detection by Diverse Data and Duplicated Instructions
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits
Journal of Electronic Testing: Theory and Applications
Embedded Robustness IPs for Transient-Error-Free ICs
IEEE Design & Test
Concurrent Error Detection Using Watchdog Processors-A Survey
IEEE Transactions on Computers
Performance Evaluation of Checksum-Based ABFT
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Soft-Error Detection Using Control Flow Assertions
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Hybrid Soft Error Detection by Means of Infrastructure IP Cores
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Algorithm-Based Fault Tolerance for Matrix Operations
IEEE Transactions on Computers
An Approach to Concurrent Control Flow Checking
IEEE Transactions on Software Engineering
The N-Version Approach to Fault-Tolerant Software
IEEE Transactions on Software Engineering
Guest editor's introduction: what is infrastructure IP?
IEEE Design & Test
An optimized hybrid approach to provide fault detection and correction in SoCs
Proceedings of the 20th annual conference on Integrated circuits and systems design
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
Journal of Electronic Testing: Theory and Applications
An industrial perspective of power-aware reliable SoC design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A compiler-based infrastructure for fault-tolerant co-design
Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems
Proceedings of the 24th symposium on Integrated circuits and systems design
Soft core based embedded systems in critical aerospace applications
Journal of Systems Architecture: the EUROMICRO Journal
An hybrid architecture to detect transient faults in microprocessors: an experimental validation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 14.98 |
Hardening SoCs against transient faults requires new techniques able to combine high fault detection capabilities with the usual requirements of SoC design flow, e.g., reduced design-time, low area overhead, and reduced (or null) accessibility to source core descriptions. This paper proposes a new hybrid approach which combines hardening software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results, including comparisons with previous approaches, are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory, and performance overheads.