Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs

Authors:
Eduardo Luis Rhod;Carlos Arthur Lisbôa;Luigi Carro;Matteo Sonza Reorda;Massimo Violante
Affiliations:
Escola de Engenharia, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil;Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil;Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil;Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy;Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2008

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Abstract

Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware hardening is not cost-effective, software implemented hardware fault tolerance (SIHFT) can be a solution to increase SoCs' dependability, but it increases the time for running the hardened application, as well as the memory occupation. In this paper we propose a method that eliminates the memory overhead, by exploiting a new approach to instruction hardening and control flow checking. The proposed method hardens an application online during its execution, without the need for introducing any change in its source code, and is non-intrusive, since it does not require any modification in the main processor's architecture. The method has been tested with two widely used architectures: a microcontroller and a RISC processor, and proven to be suitable for hardening SoCs against transient faults and also for detecting permanent faults.