A VLIW low power Java processor for embedded applications
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Application of Binary Translation to Java Reconfigurable Architectures
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Proceedings of the 42nd annual Design Automation Conference
Going beyond TMR for protection against multiple faults
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Exploiting Java through binary translation for low power embedded reconfigurable systems
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Hardware support in a middleware for distributed and real-time embedded applications
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
A low-SER efficient core processor architecture for future technologies
Proceedings of the conference on Design, automation and test in Europe
Model driven engineering for MPSOC design space exploration
Proceedings of the 20th annual conference on Integrated circuits and systems design
JTRES '07 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
Journal of Electronic Testing: Theory and Applications
Applying neural networks to performance estimation of embedded software
Journal of Systems Architecture: the EUROMICRO Journal
Dynamic task allocation strategies in MPSoC for soft real-time applications
Proceedings of the conference on Design, automation and test in Europe
Evaluation of a hardware transactional memory model in an NoC-based embedded MPSoC
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Reconfiguration of embedded java applications
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Dynamic clustering for distinct parallel programming models on NoC-based MPSoCs
Proceedings of the 4th International Workshop on Network on Chip Architectures
| Hi-index | 0.00 |
This paper presents a cycle-accurate and configurable simulator that estimates the power consumed by an embedded system. The simulator accepts as input a structural system architecture description, at a level of abstraction that can be configured by the user. The simulator has been used to study the power dissipation of different micro-architectures of a Java microcontroller while executing several applications. Thanks to the cycle-driven behavior and the structural system description, the simulator is both flexible and accurate, and it may be also fast, depending on the desired level of abstraction. It represents a valuable support in a design space exploration methodology, allowing a power consumption evaluation that can be applied to any processor and system architecture at an early design stage.