Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
DAISY: dynamic compilation for 100% architectural compatibility
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IEEE Design & Test
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FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
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SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
A VLIW low power Java processor for embedded applications
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
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In this paper we present the impact of applying binary translation to a reconfigurable architecture able to execute Java bytecodes. Besides ensuring software compatibility and porting for different machines tracking technological evolutions, the dynamic transformation of any sequence of instructions in combinational logic allows for meaningful energy savings andis totally transparent for the software designer. Moreover, we can speed up even code without a high level of parallelism available, in order of 3.5 times on average, and up to 6.5 times, spending 14 times less energy, in average. We present first studies about the impact on power and area of this technique and compare our architecture with a couple of other Java architectures, including a VLIW one. Our work uses a coarse-grain array, ensuring fast reconfiguration and less control overhead.