A high-performance microarchitecture with hardware-programmable functional units
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Applied cryptography (2nd ed.): protocols, algorithms, and source code in C
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A DAG-based design approach for reconfigurable VLIW processors
DATE '99 Proceedings of the conference on Design, automation and test in Europe
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FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
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FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
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FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
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IEEE Transactions on Parallel and Distributed Systems
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Journal of Systems Architecture: the EUROMICRO Journal
Enhancing the performance of symmetric-key cryptography via instruction set extensions
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We propose a smart compilation chain in which the compiler is no longer limited by a pre-defined instruction set, but can generate application-specific custom instructions and synthesize them in Field-Programmable Logic. We also present a RISC micro-architecture enhanced by a CPLD-based Reconfigurable Functional Unit (RFU) which supports our compiler approach. The main difference between our smart compiler and similar methods is the ability to encode multiple custom instructions in a singleRFU configuration, cross-minimizing the logic among them. The objective is to reduce (or eliminate) the reconfiguration overhead and optimize the utilization of resources. The CPLD core that implements the RFU is based on the Philips XPLA2 architecture.We discuss the advantages of using the XPLA2 instead of conventional FPGAs. Application examples are also presented, which show that our RFU-extended CPU can achieve speed-ups of more than 40% for encryption algorithms, when compared to the standard CPU core alone.