The transformation schema: An extension of the data flow diagram to represent control and timing
IEEE Transactions on Software Engineering
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Partitioning by regularity extraction
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
Generating instruction sets and microarchitectures from applications
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
SUIF: an infrastructure for research on parallelizing and optimizing compilers
ACM SIGPLAN Notices
Synthesis of instruction sets for pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
Incorporating speculative execution in exact control-dependent scheduling
DAC '94 Proceedings of the 31st annual Design Automation Conference
Instruction-level parallel processors
Instruction-level parallel processors
Parallel recombinative simulated annealing: a genetic algorithm
Parallel Computing
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Graph Isomorphism and Identification Matrices: Parallel Algorithms
IEEE Transactions on Parallel and Distributed Systems
Design Automation for Embedded Systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A simulation tool for dynamically reconfigurable field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 1995 IEEE ASIC conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Instruction set definition and instruction selection for ASIPs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
An architectural co-synthesis algorithm for distributed, embedded computing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Superblock formation using static program analysis
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Embedded system synthesis by timing constraints solving
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Solving covering problems using LPR-based lower bounds
DAC '97 Proceedings of the 34th annual Design Automation Conference
Static timing analysis of embedded software
DAC '97 Proceedings of the 34th annual Design Automation Conference
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Design space exploration algorithm for heterogeneous multi-processor embedded system design
DAC '98 Proceedings of the 35th annual Design Automation Conference
MetaCore: an application specific DSP development system
DAC '98 Proceedings of the 35th annual Design Automation Conference
A hardware/software prototyping environment for dynamically reconfigurable embedded systems
Proceedings of the 6th international workshop on Hardware/software codesign
Improving functional density using run-time circuit reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Space-time scheduling of instruction-level parallelism on a raw machine
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Memory interfacing and instruction specification for reconfigurable processors
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
COSYN: hardware-software co-synthesis of heterogeneous distributed embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
Synthesis of Application Specific Instructions for Embedded DSP Software
IEEE Transactions on Computers
Kernel scheduling in reconfigurable computing
DATE '99 Proceedings of the conference on Design, automation and test in Europe
DATE '99 Proceedings of the conference on Design, automation and test in Europe
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A DAG-based design approach for reconfigurable VLIW processors
DATE '99 Proceedings of the conference on Design, automation and test in Europe
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Reconfigurable computing: what, why, and implications for design automation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hardware-software co-design of embedded reconfigurable architectures
Proceedings of the 37th Annual Design Automation Conference
Lx: a technology platform for customizable VLIW embedded processing
Proceedings of the 27th annual international symposium on Computer architecture
Adapting software pipelining for reconfigurable computing
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
Communicating sequential processes
Communications of the ACM
Evaluation of the streams-C C-to-FPGA compiler: an applications perspective
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
A HW/SW partitioning algorithm for dynamically reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Heuristic datapath allocation for multiple wordlength systems
Proceedings of the conference on Design, automation and test in Europe
Optimal temporal partitioning and synthesis for reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Retargetable estimation scheme for DSP architecture selection
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Designing domain-specific processors
Proceedings of the ninth international symposium on Hardware/software codesign
An automated process for compiling dataflow graphs into reconfigurable hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Design and analysis of a dynamically reconfigurable three-dimensional FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
An algorithm for synthesis of large time-constrained heterogeneous adaptive systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Quality-driven design in the system-on-a-chip era: why and how?
Journal of Systems Architecture: the EUROMICRO Journal - Modern methods and tools in digital system design
Hardware/software instruction set configurability for system-on-chip processors
Proceedings of the 38th annual Design Automation Conference
Instruction scheduling for clustered VLIW architectures
ISSS '00 Proceedings of the 13th international symposium on System synthesis
ISSS '00 Proceedings of the 13th international symposium on System synthesis
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Retargetable compiler technology for embedded systems: tools and applications
Retargetable compiler technology for embedded systems: tools and applications
A framework for reconfigurable computing: task scheduling and context management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A compiler approach to fast hardware design space exploration in FPGA-based systems
PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
Loop Parallelization
Loop Transformations for Restructuring Compilers: The Foundations
Loop Transformations for Restructuring Compilers: The Foundations
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Processor Architecture: From Dataflow to Superscalar and Beyond
Processor Architecture: From Dataflow to Superscalar and Beyond
Scheduling Computer and Manufacturing Processes
Scheduling Computer and Manufacturing Processes
Multi-Objective Optimization Using Evolutionary Algorithms
Multi-Objective Optimization Using Evolutionary Algorithms
Efficient scheduling of conditional behaviors for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Datapath merging and interconnection sharing for reconfigurable architectures
Proceedings of the 15th international symposium on System Synthesis
Instruction generation and regularity extraction for reconfigurable processors
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Instruction generation for hybrid reconfigurable systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Configuration relocation and defragmentation for run-time reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Garp Architecture and C Compiler
Computer
Scheduling for Embedded Real-Time Systems
IEEE Design & Test
FlexWare: A Retargetable Embedded-Software Development Environment
IEEE Design & Test
Reconfigurable Instruction Set Processors from a Hardware/Software Perspective
IEEE Transactions on Software Engineering
Petri Nets for System Engineering: A Guide to Modeling, Verification, and Applications
Petri Nets for System Engineering: A Guide to Modeling, Verification, and Applications
Analysis of conditional resource sharing using a guard-based control representation
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Compiling SA-C Programs to FPGAs: Performance Results
ICVS '01 Proceedings of the Second International Workshop on Computer Vision Systems
JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
DEFACTO: A Design Environment for Adaptive Computing Technology
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
Lectures on Petri Nets I: Basic Models, Advances in Petri Nets, the volumes are based on the Advanced Course on Petri Nets
Instruction-Level Parallelism for Reconfigurable Computing
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Using PARBIT to Implement Partial Run-Time Reconfigurable Systems
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Compiling Application-Specific Hardware
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Implementation Approaches for Reconfigurable Logic Applications
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Very Large Scale Spatial Computing
UMC '02 Proceedings of the Third International Conference on Unconventional Models of Computation
HW/SW codesign techniques for dynamically reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis of custom processors based on extensible platforms
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
FPGA resource and timing estimation from Matlab execution traces
Proceedings of the tenth international symposium on Hardware/software codesign
Proceedings of the tenth international symposium on Hardware/software codesign
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
Using estimates from behavioral synthesis tools in compiler-directed design space exploration
Proceedings of the 40th annual Design Automation Conference
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Profiling tools for hardware/software partitioning of embedded applications
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
High-Level Synthesis of Nonprogrammable Hardware Accelerators
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Constraints-driven scheduling and resource assignment
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A unified scheduling model for high-level synthesis and code generation
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Graph Based Processor Model for Retargetable Code Generation
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Hardware/Software Partitioning using Integer Programming
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Design of an Optimal Loosely Coupled Heterogeneous Multiprocessor System
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Retargetable Generation of Code Selectors from HDL Processor Models
EDTC '97 Proceedings of the 1997 European conference on Design and Test
PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
An evolutionary approach to system-level synthesis
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
An Approach to Mixed Systems Co-Synthesis
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Temporal Partitioning and Scheduling for Reconfigurable Computing
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Parallelizing Applications into Silicon
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Stream-Oriented FPGA Computing in the Streams-C High Level Language
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Configuration Caching Management Techniques for Reconfigurable Computing
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Coarse-Grain Pipelining on Multiple FPGA Architectures
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Hardware Software Partitioning Using Genetic Algorithm
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Processor Evaluation in an Embedded Systems Design Environment
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Fpga Hardware Synthesis From Matlab
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Framework for Scheduling and Context Allocation in Reconfigurable Computing
Proceedings of the 12th international symposium on System synthesis
Low-power high-level synthesis for FPGA architectures
Proceedings of the 2003 international symposium on Low power electronics and design
Accurate Area and Delay Estimators for FPGAs
Proceedings of the conference on Design, automation and test in Europe
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
System-level codesign of mixed hardware-software systems
System-level codesign of mixed hardware-software systems
Hierarchical Conditional Dependency Graphs for Conditional Resource Sharing
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Automated Synthesis of Interleaved Memory Systems for Custom Computing Machines
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Computer
Automatic compilation to a coarse-grained reconfigurable system-opn-chip
ACM Transactions on Embedded Computing Systems (TECS)
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Advanced AI Search Techniques in Modern Digital Circuit Synthesis
Artificial Intelligence Review
Polymorphous fabric-based systems: model, tools, applications
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Application-specific instruction generation for configurable processor architectures
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Reconfigurable platforms for ubiquitous computing
Proceedings of the 1st conference on Computing frontiers
Macro-models for high level area and power estimation on FPGAs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
An optimal algorithm for minimizing run-time reconfiguration delay
ACM Transactions on Embedded Computing Systems (TECS)
Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling
ACM Transactions on Embedded Computing Systems (TECS)
An area estimation methodology for FPGA based designs at systemc-level
Proceedings of the 41st annual Design Automation Conference
Characterizing embedded applications for instruction-set extensible processors
Proceedings of the 41st annual Design Automation Conference
Introduction of local memory elements in instruction set extensions
Proceedings of the 41st annual Design Automation Conference
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Scalable Application-Specific Processor Synthesis Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Resource Estimation and Task Scheduling for Multithreaded Reconfigurable Architectures
ICPADS '04 Proceedings of the Parallel and Distributed Systems, Tenth International Conference
Synthesizable HDL generation method for configurable VLIW processors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Task scheduling for heterogeneous reconfigurable computers
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Power-performance trade-offs for reconfigurable computing
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Scalable custom instructions identification for instruction-set extensible processors
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
Design Patterns for Reconfigurable Computing
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Register Binding for FPGAs with Embedded Memory
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Efficient metrics and high-level synthesis for dynamically reconfigurable logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Instruction set extension with shadow registers for configurable processors
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Optimized Generation of Data-Path from C Codes for FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Configuration Compression for Virtex FPGAs
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fine-grained application source code profiling for ASIP design
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Effective bounding techniques for solving unate and binate covering problems
Proceedings of the 42nd annual Design Automation Conference
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Proceedings of the 32nd annual international symposium on Computer Architecture
Automated Custom Instruction Generation for Domain-Specific Processor Acceleration
IEEE Transactions on Computers
Satisfying real-time constraints with custom instructions
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An integer linear programming approach for identifying instruction-set extensions
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An automated exploration framework for FPGA-based soft multiprocessor systems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
Exploiting pipelining to relax register-file port constraints of instruction-set extensions
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Exploring the design space of LUT-based transparent accelerators
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices
IEEE Design & Test
A Reconfiguration Manager for Dynamically Reconfigurable Hardware
IEEE Design & Test
A Constraints Programming Approach for Fabric Cell Synthesis
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
An Efficient Approach to Custom Instruction Set Generation
RTCSA '05 Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Structured Development for Real-Time Systems
Structured Development for Real-Time Systems
Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Optimizing Register Binding in FPGAs Using Simulated Annealing
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
Power-aware RAM mapping for FPGA embedded memory blocks
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Application-specific customization of soft processor microarchitecture
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Bitwidth-aware scheduling and binding in high-level synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Compile-time area estimation for LUT-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Exploiting forwarding to improve data bandwidth of instruction-set extensions
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 2006 international symposium on Low power electronics and design
A Platform-Based Taxonomy for ESL Design
IEEE Design & Test
Automatic selection of application-specific instruction-set extensions
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Code transformation strategies for extensible embedded processors
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Optimized ASIP Synthesis from Architecture Description Language Models
Optimized ASIP Synthesis from Architecture Description Language Models
Co-design for System Acceleration: A Quantitative Approach
Co-design for System Acceleration: A Quantitative Approach
Customizable Embedded Processors: Design Technologies and Applications
Customizable Embedded Processors: Design Technologies and Applications
Building ASIPs: The Mescal Methodology
Building ASIPs: The Mescal Methodology
Support for partial run-time reconfiguration of platform FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
Mapping data-parallel tasks onto partially reconfigurable hybrid processor architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integration, the VLSI Journal - Special issue: Embedded cryptographic hardware
Platform-based resource binding using a distributed register-file microarchitecture
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Journal of Embedded Computing - Cache exploitation in embedded systems
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs
Journal of Systems Architecture: the EUROMICRO Journal
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Application Specific Datapath Extension with Distributed I/O Functional Units
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Proceedings of the conference on Design, automation and test in Europe
Optimizing instruction-set extensible processors under data bandwidth constraints
Proceedings of the conference on Design, automation and test in Europe
Polynomial-time subgraph enumeration for automated instruction set extension
Proceedings of the conference on Design, automation and test in Europe
Design methodology for pipelined heterogeneous multiprocessor system
Proceedings of the 44th annual Design Automation Conference
Static scheduling techniques for dependent tasks on dynamically reconfigurable devices
Journal of Systems Architecture: the EUROMICRO Journal
Rethinking custom ISE identification: a new processor-agnostic method
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
An efficient framework for dynamic reconfiguration of instruction-set customization
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Trace Scheduling: A Technique for Global Microcode Compaction
IEEE Transactions on Computers
A novel SoC design methodology combining adaptive software and reconfigurable hardware
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Efficient ASIP design for configurable processors with fine-grained resource sharing
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
The shining embedded system design methodology based on self dynamic reconfigurable architectures
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
An incremental temporal partitioning method for real-time reconfigurable systems
EHAC'06 Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Quality-driven model-based architecture synthesis for real-time embedded SoCs
Journal of Systems Architecture: the EUROMICRO Journal
Application partitioning on programmable platforms using the ant colony optimization
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
A Flexible system level design methodology targeting run-time reconfigurable FPGAs
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
Hardware Synthesis for Reconfigurable Heterogeneous Pipelined Accelerators
ITNG '08 Proceedings of the Fifth International Conference on Information Technology: New Generations
Automatic selection of application-specific reconfigurable processor extensions
Proceedings of the conference on Design, automation and test in Europe
Rapid design of area-efficient custom instructions for reconfigurable embedded processing
Journal of Systems Architecture: the EUROMICRO Journal
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems
Microprocessors & Microsystems
A holistic approach for tightly coupled reconfigurable parallel processors
Microprocessors & Microsystems
3D configuration caching for 2D FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays
SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
NP-complete scheduling problems
Journal of Computer and System Sciences
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Requirements on the execution of Kahn process networks
ESOP'03 Proceedings of the 12th European conference on Programming
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Automatic application-specific microarchitecture reconfiguration
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Morphable structures for reconfigurable instruction set processors
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
IEEE Transactions on Computers
Force-directed scheduling for the behavioral synthesis of ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wavesched: a novel scheduling technique for control-flow intensive designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path-based scheduling for synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Custom-instruction synthesis for extensible-processor platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Flamel: A High-Level Hardware Compiler
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact and approximate algorithms for the extension of embedded processor instruction sets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ASC: a stream compiler for computing with FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast Identification of Custom Instructions for Extensible Processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA Pipeline Synthesis Design Exploration Using Module Selection and Resource Sharing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Introduction of Architecturally Visible Storage in Instruction Set Extensions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CHIPS: Custom Hardware Instruction Processor Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accelerating loops for coarse grained reconfigurable architectures using instruction extensions
Proceedings of the 2011 ACM Symposium on Research in Applied Computation
Real-time reconfigurable SoC for process control
International Journal of Computer Applications in Technology
Static routing for applications mapped on NoC platform using ant colony algorithms
International Journal of High Performance Systems Architecture
Scalable communication architectures for massively parallel hardware multi-processors
Journal of Parallel and Distributed Computing
Expert Systems with Applications: An International Journal
Hardware reuse in modern application-specific processors and accelerators
Microprocessors & Microsystems
Physicality quantitative evaluation method
Proceedings of the 25th Australian Computer-Human Interaction Conference: Augmentation, Application, Innovation, Collaboration
Design of massively parallel hardware multi-processors for highly-demanding embedded applications
Microprocessors & Microsystems
ASAM: Automatic architecture synthesis and application mapping
Microprocessors & Microsystems
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Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumption than traditional CPU-centric systems. Moreover, they do it at much lower costs and shorter times to market than non-reconfigurable hardware solutions. They also provide the flexibility that is often required for the engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, reconfigurable systems are adequate for a very broad class of applications across different industry sectors. What prevents the reconfigurable system paradigm from a broad proliferation is the lack of adequate development methodologies and electronics design tools for this kind of systems. The ideal would be a seamless compilation of a high-level computation process specification into an optimized mixture of machine code executed on traditional CPU-centric processors and on the application-specific decentralized parallel data-flow-dominated reconfigurable processors and hardware accelerators. Although much research and development in this direction was recently performed, the adequate methodologies and tools necessary to implement this compilation process as an effective and efficient hardware/software co-synthesis flow are unfortunately not yet in place. This paper focuses on the recent developments and development trends in the design methods and synthesis tools for reconfigurable systems. Reconfigurable system synthesis performs two basic tasks: system structure construction and application process mapping on the structure. It is thus more complex than standard (multi-)processor-based system synthesis for software-programmable systems that only involves application mapping. The system structure construction may involve the macro-architecture synthesis, the micro-architecture synthesis, and the actual hardware synthesis. Also, the application process mapping can be more complicated and dynamic in reconfigurable systems. This paper reviews the recent methods and tools for the macro- and micro-architecture synthesis, and for the application mapping of reconfigurable systems. It puts much attention to the relevant and currently hot topic of (re-)configurable application-specific instruction set processors (ASIP) synthesis, and specifically, ASIP instruction set extension. It also discusses the methods and tools for reconfigurable systems involving CPU-centric processors collaborating with reconfigurable hardware sub-systems, for which the main problem is to decide which computation processes should be implemented in software and which in hardware, but the hardware/software partitioning has to account for the hardware sharing by different computation processes and for the reconfiguration processes. The reconfigurable system area is a very promising, but quite a new field, with many open research and development topics. The paper reviews some of the future trends in the reconfigurable system development methods and tools. Finally, the discussion of the paper is summarized and concluded.