Hardware/software instruction set configurability for system-on-chip processors

Authors:
Albert Wang;Earl Killian;Dror Maydan;Chris Rowen
Affiliations:
Tensilica, Inc., 3255-6 Scott Blvd., Santa Clara, CA;Tensilica, Inc., 3255-6 Scott Blvd., Santa Clara, CA;Tensilica, Inc., 3255-6 Scott Blvd., Santa Clara, CA;Tensilica, Inc., 3255-6 Scott Blvd., Santa Clara, CA
Venue:
Proceedings of the 38th annual Design Automation Conference
Year:
2001

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Abstract

New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned logic solutions with the flexibility of standard high-level programming methodology. Automated extension of processor function units and the associated software environment - compilers, debuggers, simulators and real-time operating systems - satisfies these needs. At the same time, designing at the level of software and instruction set architecture significantly shortens the design cycle and reduces verification effort and risk. This paper describes the key dimensions of extensibility within the processor architecture, the instruction set extension description language and the means of automatically extending the software environment from that description. It also describes two groups of benchmarks, EEMBC's Consumer and Telecommunications suites, that show 20 to 40 times acceleration of a broad set of algorithms through application-specific instruction set extension, relative to high performance RISC processors.