Hardware/software instruction set configurability for system-on-chip processors
Proceedings of the 38th annual Design Automation Conference
Vector processing as an enabler for software-defined radio in handheld devices
EURASIP Journal on Applied Signal Processing
Implementation of W-CDMA Cell Search on a Highly Parallel and Scalable MPSoC
Journal of Signal Processing Systems
Configurability in IP subystems: baseband examples
Proceedings of the Conference on Design, Automation and Test in Europe
A flexible and fast software implementation of the FFT on the BPE platform
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A complexity adaptive channel estimator for low power
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The high computation demands of next generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. This paper introduces a new DSP architecture optimized for baseband applications, especially applications with heavy workload of complex filtering, FFT and MIMO matrix operations such as LTE. The Tensilica ConnX Baseband Engine processor core implements a 3-issue VLIW, 8-way SIMD architecture. It can perform 16 multiply-add operations per cycle, and executes a full radix-4 FFT butterfly or 4 complex FIR filter taps per cycle. It directly implements vector division and reciprocal square root operations. At 400MHz, it provides almost 13GB per second of memory bandwidth. The rich programming environment, including vectorization of scalar C applications, allows easy deployment into cellular base-station, femto-cell and other software-agile radio applications, and into multistandard broadcast receivers.