Verification of configurable processor cores
Proceedings of the 37th Annual Design Automation Conference
Micronetwork-based integration for SOCs: 673
Proceedings of the 38th annual Design Automation Conference
Design of a Virtual Component Neutral Network-on-Chip Transaction Layer
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Customizable Embedded Processors: Design Technologies and Applications
Customizable Embedded Processors: Design Technologies and Applications
Processor Description Languages
Processor Description Languages
A DSP architecture optimized for wireless baseband
SOC'09 Proceedings of the 11th international conference on System-on-chip
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Configurability in IP subsystems has two major motivations. The first is the requirements of the IP subsystem itself; the second the particular customer requirements, as every customer has unique things they want to change in a subsystem. Configurability manifests itself at two levels - the individual components, such as processors (ideally configurable), memories, and hardware blocks for specialized processing; the second one at the subsystem level, where component choices, interconnect and interfaces may all vary considerably. This paper discusses these concepts applied to practical, real, baseband subsystems for wireless communications. Configurability allows both scalability of a reference IP subsystem - e.g. to handle varieties of standards and use cases; and differentiation, so that customers get the optimal IP subsystem for their unique needs. This is illustrated with existing product-ready systems and cores, and future subsystem concepts that will allow even better scalability, performance, and adaptability for the next generation.