Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
An algorithm for the synthesis of processor structures from behavioural specifications
Microprocessing and Microprogramming
A VLIW architecture for a trace scheduling compiler
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
SAMP: a general purpose processor based on a self-timed VLIW structure
ACM SIGARCH Computer Architecture News
SSIM: a software levelized compiled-code simulator
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Integrated scheduling and binding: a synthesis approach for design space exploration
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Verification of hardware descriptions by retargetable code generation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Structured logic design with VHDL
Structured logic design with VHDL
Symbolic simulation—techniques and applications
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
BURG: fast optimal instruction selection and tree parsing
ACM SIGPLAN Notices
Engineering a simple, efficient code-generator generator
ACM Letters on Programming Languages and Systems (LOPLAS)
Shade: a fast instruction-set simulator for execution profiling
SIGMETRICS '94 Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Attribute grammar paradigms—a high-level methodology in language implementation
ACM Computing Surveys (CSUR)
A formal model and specification language for procedure calling conventions
POPL '95 Proceedings of the 22nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Retargetable self-test program generation using constraint logic programming
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A hardware/software partitioning algorithm for pipelined instruction set processor
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Embra: fast and flexible machine simulation
Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Evolving algebras 1993: Lipari guide
Specification and validation methods
Graph based retargetable microcode compilation in the MIMOLA design system
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Specifying representations of machine instructions
ACM Transactions on Programming Languages and Systems (TOPLAS)
Tree-based mapping of algorithms to predefined structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A new optimization technique for improving resource exploitation and critical path minization
ISSS '97 Proceedings of the 10th international symposium on System synthesis
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
Generation of software tools from processor descriptions for hardware/software codesign
DAC '97 Proceedings of the 34th annual Design Automation Conference
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
A framework for classifying and comparing architecture description languages
ESEC '97/FSE-5 Proceedings of the 6th European SOFTWARE ENGINEERING conference held jointly with the 5th ACM SIGSOFT international symposium on Foundations of software engineering
Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator
DAC '98 Proceedings of the 35th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
The Verilog hardware description language (4th ed.)
The Verilog hardware description language (4th ed.)
A processor desription language supporting retargetable multi-pipeline DSP program development tools
Proceedings of the 11th international symposium on System synthesis
Combinational equivalence checking using satisfiability and recursive learning
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A retargetable, ultra-fast instruction set simulator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A methodology for accurate performance evaluation in architecture exploration
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
LISA—machine description language for cycle-accurate models of programmable DSP architectures
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new synthesis for the MIMOLA software system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic generation of self-test programs—a new feature of the MIMOLA design system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Memory aware compilation through accurate timing extraction
Proceedings of the 37th Annual Design Automation Conference
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
Retargetable Compiler Code Generation
ACM Computing Surveys (CSUR)
Retargetable compiled simulation of embedded processors using a machine description language
ACM Transactions on Design Automation of Electronic Systems (TODAES)
PRMDL: a machine description language for clustered VLIW architectures
Proceedings of the conference on Design, automation and test in Europe
Sequential equivalence checking without state space traversal
Proceedings of the conference on Design, automation and test in Europe
Communications of the ACM
Hardware/software instruction set configurability for system-on-chip processors
Proceedings of the 38th annual Design Automation Conference
Optimal spilling for CISC machines with few registers
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
Processor modeling and code selection for retargetable compilation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
APEX: access pattern based memory architecture exploration
Proceedings of the 14th international symposium on Systems synthesis
Functional abstraction driven design space exploration of heterogeneous programmable architectures
Proceedings of the 14th international symposium on Systems synthesis
Design space characterization for architecture/compiler co-exploration
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
A new method for compiler code generation
POPL '78 Proceedings of the 5th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
A practical and efficient method for compare-point matching
Proceedings of the 39th annual Design Automation Conference
System Design with SystemC
VHDL: Programming by Example
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Ella 2000: A Language for Electronic System Design
Ella 2000: A Language for Electronic System Design
Efficient architecture/compiler co-exploration for ASIPs
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
MIST: an algorithm for memory miss traffic management
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Access pattern-based memory and connectivity architecture exploration
ACM Transactions on Embedded Computing Systems (TECS)
Design and Development Paradigm for Industrial Formal Verification CAD Tools
IEEE Design & Test
A Heterogeneous Multiprocessor Architecture for Flexible Media Processing
IEEE Design & Test
Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
Limited Bandwidth to Affect Processor Design
IEEE Micro
Instruction-Based Self-Testing of Processor Cores
Journal of Electronic Testing: Theory and Applications
Architecture Exploration for Embedded Processors with Lisa
Architecture Exploration for Embedded Processors with Lisa
Instruction Scheduler Generation for Retargetable Compilation
IEEE Design & Test
Implementations of IF-statements in the TODOS microarchitecture synthesis system
Proceedings of the IFIP WG10.2/WG10.5 Workshops on Synthesis for Control Dominated Circuits
Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions
DIPES '02 Proceedings of the IFIP 17th World Computer Congress - TC10 Stream on Distributed and Parallel Embedded Systems: Design and Analysis of Distributed Embedded Systems
Instruction encoding synthesis for architecture exploration using hierarchical processor models
Proceedings of the 40th annual Design Automation Conference
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Proceedings of the 40th annual Design Automation Conference
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Retargetable Generation of Code Selectors from HDL Processor Models
EDTC '97 Proceedings of the 1997 European conference on Design and Test
MIPS: A microprocessor architecture
MICRO 15 Proceedings of the 15th annual workshop on Microprogramming
A retargetable microcode generation system for a high-level microprogramming language
MICRO 14 Proceedings of the 14th annual workshop on Microprogramming
DAC '80 Proceedings of the 17th Design Automation Conference
A retargetable compiler for a high-level microprogramming language
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
The MIMOLA design system a computer aided digital processor design method
DAC '79 Proceedings of the 16th Design Automation Conference
The MIMOLA design system: Detailed description of the software system
DAC '79 Proceedings of the 16th Design Automation Conference
Instruction set processor specifications for simulation, evaluation, and synthesis
DAC '79 Proceedings of the 16th Design Automation Conference
The CMU design automation system: An example of automated data path design
DAC '79 Proceedings of the 16th Design Automation Conference
Automatic Validation of Pipeline Specifications
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
Processor Modeling for Hardware Software Codesign
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Architecture Implementation Using the Machine Description Language LISA
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
PEAS-III: An ASIP Design Environment
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Automatic Generation of Microarchitecture Simulators
ICCL '98 Proceedings of the 1998 International Conference on Computer Languages
A Survey of Architecture Description Languages
IWSSD '96 Proceedings of the 8th International Workshop on Software Specification and Design
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Proceedings of the conference on Design, automation and test in Europe
Memory System Connectivity Exploration
Proceedings of the conference on Design, automation and test in Europe
Formalization and automatic derivation of code generators.
Formalization and automatic derivation of code generators.
An efficient retargetable framework for instruction-set simulation
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Matching system and component behaviour in MIMOLA synthesis tools
EURO-DAC '90 Proceedings of the conference on European design automation
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
RTGEN: an algorithm for automatic generation of reservation tables from architectural descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis-driven Exploration of Pipelined Embedded Processors
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Graph-Based Functional Test Program Generation for Pipelined Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models
Proceedings of the conference on Design, automation and test in Europe - Volume 2
RTL Processor Synthesis for Architecture Exploration and Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Modeling and validation of pipeline specifications
ACM Transactions on Embedded Computing Systems (TECS)
Processor-memory coexploration using an architecture description language
ACM Transactions on Embedded Computing Systems (TECS)
A Top-Down Methodology for Microprocessor Validation
IEEE Design & Test
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Synthesizable HDL generation method for configurable VLIW processors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Dual-pipeline heterogeneous ASIP design
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Operation tables for scheduling in the presence of incomplete bypassing
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Rapid Configuration and Instruction Selection for an ASIP: A Case Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Specification-driven validation of programmable embedded systems
Specification-driven validation of programmable embedded systems
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
ArchC: A SystemC-Based Architecture Description Language
SBAC-PAD '04 Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing
Optimizations for Compiled Simulation Using Instruction Type Information
SBAC-PAD '04 Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing
Modeling and description of embedded processors for the development of software tools
Modeling and description of embedded processors for the development of software tools
Software-Based Self-Testing of Embedded Processors
IEEE Transactions on Computers
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
C Compiler Retargeting Based on Instruction Semantics Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Optimization Techniques for ADL-Driven RTL Processor Synthesis
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
Closing the POWER Gap between ASIC & Custom: Tools and Techniques for Low Power Design
Closing the POWER Gap between ASIC & Custom: Tools and Techniques for Low Power Design
A cycle-accurate compilation algorithm for custom pipelined datapaths
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Aggregating processor free time for energy reduction
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Micro embedded monitoring for security in application specific instruction-set processors
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores
MTV '04 Proceedings of the Fifth International Workshop on Microprocessor Test and Verification
Extending the ArchC Language for Automatic Generation of Assemblers
SBAC-PAD '05 Proceedings of the 17th International Symposium on Computer Architecture on High Performance Computing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Compilation framework for code size reduction using reduced bit-width ISAs (rISAs)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test generation using SAT-based bounded model checking for validation of pipelined processors
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Combining simulation and formal methods for system-level performance analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Automatic ADL-based operand isolation for embedded processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An integrated open framework for heterogeneous MPSoC design space exploration
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Functional test generation using property decompositions for validation of pipelined processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Integrated Verification Approach during ADL-Driven Processor Design
RSP '06 Proceedings of the Seventeenth IEEE International Workshop on Rapid System Prototyping
Proceedings of the 41st annual Design Automation Conference
The ArchC architecture description language and tools
International Journal of Parallel Programming
A retargetable framework for instruction-set architecture simulation
ACM Transactions on Embedded Computing Systems (TECS)
Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Retargetable code optimization with SIMD instructions
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Application specific forwarding network and instruction encoding for multi-pipe ASIPs
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
SystemC: From the Ground Up
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Functional Verification of Programmable Embedded Architectures: A Top-Down Approach
Functional Verification of Programmable Embedded Architectures: A Top-Down Approach
FPGA-friendly code compression for horizontal microcoded custom IPs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Fast construction of test-program generators for digital signal processors
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04
Trailblazing: A Hierarchical Approach to Percolation Scheduling
ICPP '93 Proceedings of the 1993 International Conference on Parallel Processing - Volume 02
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Automatic Retargeting of Binary Utilities for Embedded Code Generation
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
MTV '06 Proceedings of the Seventh International Workshop on Microprocessor Test and Verification
A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation
RSP '07 Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping
Power-efficient Instruction Encoding Optimization for Embedded Processors
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow
Proceedings of the conference on Design, automation and test in Europe
Efficient event-driven simulation of parallel processor architectures
SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems
HySim: a fast simulation framework for embedded software development
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A computational reflection mechanism to support platform debugging in SystemC
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Computers
The MPG System: A Machine-Independent Efficient Microprogram Generator
IEEE Transactions on Computers
Functional Testing of Microprocessors
IEEE Transactions on Computers
Test Generation for Microprocessors
IEEE Transactions on Computers
Increasing data-bandwidth to instruction-set extensions through register clustering
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Verification Driven Formal Architecture and Microarchitecture Modeling
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
No-instruction-set-computer (nisc) technology modeling and compilation
No-instruction-set-computer (nisc) technology modeling and compilation
Synthesis and optimization of low-power custom nisc processors
Synthesis and optimization of low-power custom nisc processors
Modeling of interconnection networks in massively parallel processor architectures
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
Automated generation of DSP program development tools using a machine description formalism
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
Instruction set processor specifications (ISPS): the notation and its applications
IEEE Transactions on Computers
Trimaran: an infrastructure for research in instruction-level parallelism
LCPC'04 Proceedings of the 17th international conference on Languages and Compilers for High Performance Computing
Specification-based compaction of directed tests for functional validation of pipelined processors
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
TotalProf: a fast and accurate retargetable source code profiler
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Automatic generation of memory interfaces
SOC'09 Proceedings of the 11th international conference on System-on-chip
Versatile system-level memory-aware platform description approach for embedded MPSoCs
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Functional test generation using efficient property clustering and learning techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
What is a configurable, extensible processor?
ACM SIGDA Newsletter
What is a configurable, extensible processor?
ACM SIGDA Newsletter
Enforcing architectural contracts in high-level synthesis
Proceedings of the 48th Design Automation Conference
The Java Virtual Machine in retargetable, high-performance instruction set simulation
Proceedings of the 9th International Conference on Principles and Practice of Programming in Java
Journal of Systems Architecture: the EUROMICRO Journal
Processor design using a functional hardware description language
Microprocessors & Microsystems
Fine-grained hardware/software methodology for process migration in MPSoCs
Proceedings of the International Conference on Computer-Aided Design
Automatic Generation of Memory Interfaces for ASIPs
International Journal of Embedded and Real-Time Communication Systems
Configurability in IP subystems: baseband examples
Proceedings of the Conference on Design, Automation and Test in Europe
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors
Proceedings of the Conference on Design, Automation and Test in Europe
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors
Proceedings of the 50th Annual Design Automation Conference
Reli: hardware/software checkpoint and recovery scheme for embedded processors
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems
Proceedings of the International Conference on Computer-Aided Design
Automated generation of efficient instruction decoders for instruction set simulators
Proceedings of the International Conference on Computer-Aided Design
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Efficient design of embedded processors plays a critical role in embedded systems design. Processor description languages and their associated specification, exploration and rapid prototyping methodologies are used to find the best possible design for a given set of applications under various design constraints, such as area, power and performance. This book is the first, comprehensive survey of modern architecture description languages and will be an invaluable reference for embedded system architects, designers, developers, and validation engineers. Readers will see that the use of particular architecture description languages will lead to productivity gains in designing particular (application-specific) types of embedded processors.* Comprehensive coverage of all modern architecture description languages... use the right ADL to design your processor to fit your application;* Most up-to-date information available about each architecture description language from the developers...save time chasing down reliable documentation;* Describes how each architecture desccription language enables key design automation tasks, such as simulation, synthesis and testing...fit the ADL to your design cycle;