Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Application-specific customization of soft processor microarchitecture
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Automatic ADL-based operand isolation for embedded processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Generic netlist representation for system and PE level design exploration
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Compiler generation from structural architecture descriptions
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Specification-driven directed test generation for validation of pipelined processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Processor Description Languages
Processor Description Languages
Automatic multithreaded pipeline synthesis from transactional datapath specifications
Proceedings of the 47th Design Automation Conference
Automatic pipelining from transactional datapath specifications
Proceedings of the Conference on Design, Automation and Test in Europe
Resource-constrained high-level datapath optimization in ASIP design
Proceedings of the Conference on Design, Automation and Test in Europe
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Recent advances on language based software toolkit generationenables performance driven exploration of embeddedsystems by exploiting the application behavior. Thereis a need for an automatic generation of hardware to determinethe required silicon area, clock frequency, and powerconsumption of the candidate architectures. In this paper,we present a language based exploration frameworkthat automatically generates synthesizable RTL models forpipelined processors. Our framework allows varied micro-architecturalmodifications, such as, addition of pipelinestages, pipeline paths, opcodes and new functional units. Thegenerated RTL is synthesized to determine the area, power,and clock frequency of the modified architectures. Our explorationresults demonstrate the power of reuse in composingheterogeneous architectures using functional abstractionprimitives allowing for a reduction in the time for specificationand exploration by at least an order of magnitude.