Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Architectural retiming: pipelining latency-constrained circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
High-level automatic pipelining for sequential circuits
Proceedings of the 14th international symposium on Systems synthesis
PEAS-III: An ASIP Design Environment
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Synthesis-driven Exploration of Pipelined Embedded Processors
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
RTL Processor Synthesis for Architecture Exploration and Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
Correct-by-construction microarchitectural pipelining
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Exploration and Customization of FPGA-Based Soft Processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic multithreaded pipeline synthesis from transactional datapath specifications
Proceedings of the 47th Design Automation Conference
CoRAM: an in-fabric memory architecture for FPGA-based computing
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
A SystemC library for specifying pipeline abstractions
Microprocessors & Microsystems
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We present a transactional datapath specification (T-spec) and the tool (T-piper) to synthesize automatically an in-order pipelined implementation from it. T-spec abstractly views a datapath as executing one transaction at a time, computing next system states based on current ones. From a T-spec, T-piper can synthesize a pipelined implementation that preserves original transaction semantics, while allowing simultaneous execution of multiple overlapped transactions across pipeline stages. T-piper not only ensures the correctness of pipelined executions, but can also employ forwarding and speculation to minimize performance loss due to data dependencies. Design case studies on RISC and CISC processor pipeline development are reported.