Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
High level synthesis of pipelined instruction set processors and back-end compilers
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Architecture synthesis of high-performance application-specific processors
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Scheduling for functional pipelining and loop winding
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Synthesis of pipelined instruction set processors
DAC '93 Proceedings of the 30th international Design Automation Conference
Architectural retiming: pipelining latency-constrained circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
High-level specification and efficient implementation of pipelined circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
Hardware Synthesis from Term Rewriting Systems
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
Combining MBP-speculative computation and loop pipelining in high-level synthesis
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Fast Specification of Cycle-Accurate Processor Models
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
High-level optimization of pipeline design
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Optimizing sequential cycles through Shannon decomposition and retiming
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Synthesizing synchronous elastic flow networks
Proceedings of the conference on Design, automation and test in Europe
Correct-by-construction microarchitectural pipelining
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Automatic multithreaded pipeline synthesis from transactional datapath specifications
Proceedings of the 47th Design Automation Conference
Automatic microarchitectural pipelining
Proceedings of the Conference on Design, Automation and Test in Europe
Automatic pipelining from transactional datapath specifications
Proceedings of the Conference on Design, Automation and Test in Europe
Task partitioning for multi-core network processors
CC'05 Proceedings of the 14th international conference on Compiler Construction
| Hi-index | 0.00 |
This paper presents a new approach for automatically pipelining sequential circuits. The approach repeatedly extracts a computation from the critical path, moves it into a new stage, then uses speculation to generate a stream of values that keep the pipeline full. The newly generated circuit retains enough state to recover from incorrect speculations by flushing the incorrect values from the pipeline, restoring the correct state, then restarting the computation.We also implement two extensions to this basic approach: stalling, which minimizes circuit area by eliminating speculation, and forwarding, which increases the throughput of the generated circuit by forwarding correct values to preceding pipeline stages. We have implemented a prototype synthesizer based on this approach. Our experimental results show that, starting with a non-pipelined or insufficiently pipelined specification, this synthesizer can effectively reduce the clock cycle time and improve the throughput of the generated circuit.