Handbook of logic in computer science (vol. 2)
Formal Modeling and Verification of Microprocessors
IEEE Transactions on Computers
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Term rewriting and all that
Commit-reconcile & fences (CRF): a new memory model for architects and compiler writers
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
CACHET: an adaptive cache coherence protocol for distributed shared-memory systems
ICS '99 Proceedings of the 13th international conference on Supercomputing
Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Testing for Function and Performance: Towards anIntegrated Processor Validation Methodology
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
High-level automatic pipelining for sequential circuits
Proceedings of the 14th international symposium on Systems synthesis
Synthesis of operation-centric hardware descriptions
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Typing Assembly Programs with Explicit Forwarding
TACS '01 Proceedings of the 4th International Symposium on Theoretical Aspects of Computer Software
A Framework for Microprocessor Correctness Statements
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Modular scheduling of guarded atomic actions
Proceedings of the 41st annual Design Automation Conference
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
A framework for systematic validation and debugging of pipeline simulators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-level synthesis: an essential ingredient for designing complex ASICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SAEPTUM: verification of ELAN hardware specifications using the proof assistant PVS
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Optimization of polynomial datapaths using finite ring algebra
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Getting Formal Verification into Design Flow
FM '08 Proceedings of the 15th international symposium on Formal Methods
Full simulation coverage for SystemC transaction-level models of systems-on-a-chip
Formal Methods in System Design
Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Towards a synthesis semantics for systemC channels
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A monadic approach to automated reasoning for Bluespec SystemVerilog
Innovations in Systems and Software Engineering
Formally defining and verifying master/slave speculative parallelization
FM'05 Proceedings of the 2005 international conference on Formal Methods
Verifying safety of a token coherence implementation by parametric compositional refinement
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
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We present a novel use of Term Rewriting Systems (TRS's) to describe micro-architectures. The state of a system is represented as a TRS term while the state transitions are represented as TRS rules. TRS descriptions are amenable to both verification and synthesis. We illustrate the use of TRS's by giving the operational semantics of a simple RISC instruction set. We then present another TRS that implements the same instruction set on a micro-architecture which permits register renaming and speculative execution. The correctness of the speculative implementation is discussed in terms of the ability of the two TRS's to simulate each other. Our method facilitates understanding of important micro-architectural differences without delving into low-level implementation details.