The existence of refinement mappings
Theoretical Computer Science
Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal Verification of a Pipelined Microprocessor
IEEE Software
Algebraic Models of Superscalar Microprocessor Implementations: A Case Study
Proceedings of the ESPRIT Working Group 8533 on Prospects for Hardware Foundations: NADA - New Hardware Design Methods, Survey Chapters
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Verification of Data-Insensitive CIrcuits: An In-Order-Retirement Case Study
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Reducing Manual Abstraction in Formal Verification of Out-of-Order Execution
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Correctness of Pipelined Machines
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
A Comparison of Two Verification Methods for Speculative Instruction Execution
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Verifying out-of-order executions
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Results of the Verification of a Complex Pipelined Machine Model
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Proof of Correctness of a Processor Implementing Tomasulo's Algorithm without a Reorder Buffer
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Trace Table Based Approach for Pipeline Microprocessor Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Formal Verification of Out-of-Order Execution Using Incremental Flushing
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
You Assume, We Guarantee: Methodology and Case Studies
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Decomposing the Proof of Correctness of pipelined Microprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verifying Advanced Microarchitectures that Support Speculation and Exceptions
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Protocol Verification by Aggregation of Distributed Transactions
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
A Correctness Model for Pipelined Multiprocessors
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
Verifying Tomasulo's Algoithm by Refinement
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Formal Verification of an ARM Processor
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Algorithms and methodology for scalable model checking
Algorithms and methodology for scalable model checking
An algebraic definition of simulation between programs
IJCAI'71 Proceedings of the 2nd international joint conference on Artificial intelligence
Relating Multi-step and Single-Step Microprocessor Correctness Statements
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
CALCO'05 Proceedings of the First international conference on Algebra and Coalgebra in Computer Science
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Most verifications of out-of-order microprocessors compare state-machine-based implementations and specifications, where the specification is based on the instruction-set architecture. The different efforts use a variety of correctness statements, implementations, and verification approaches. We present a framework for classifying correctness statements about safety that is independent of implementation representation and verification approach. We characterize the relationships between the different statements and illustrate how existing and classical approaches fit within this framework.