Synchronous circuit verification by symbolic simulation: an illustration
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
A Microprocessor-Based Implantable Telemetry System
Computer - Special issue on computer-based medical systems
Formal hardware verification by symbolic ternary trajectory evaluation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A methodology for formal hardware verification, with application to microprocessors
A methodology for formal hardware verification, with application to microprocessors
Proving circuit correctness using formal comparison between expected and extracted behaviour
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Formal Verification of a Pipelined Microprocessor
IEEE Software
Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories
Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories
Symbolic execution of formal machine descriptions
Symbolic execution of formal machine descriptions
Fm8501: a verified microprocessor (theorem-proving, computers, design)
Fm8501: a verified microprocessor (theorem-proving, computers, design)
Automatic test program generation for pipelined processors
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Automatic clock abstraction from sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Formal verification of PowerPC arrays using symbolic trajectory evaluation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification of a superscalar execution unit
DAC '97 Proceedings of the 34th annual Design Automation Conference
Toward formalizing a validation methodology using simulation coverage
DAC '97 Proceedings of the 34th annual Design Automation Conference
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Buffer-Oriented Methodology for Microarchitecture Validation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Efficient Detection of Vacuity in Temporal Model Checking
Formal Methods in System Design - Special issue on CAV '97
Handling special constructs in symbolic simulation
Proceedings of the 39th annual Design Automation Conference
Effectiveness of Microarchitecture Test Program Generation
IEEE Design & Test
Design and Development Paradigm for Industrial Formal Verification CAD Tools
IEEE Design & Test
Vacuity Checking in the Modal Mu-Calculus
AMAST '02 Proceedings of the 9th International Conference on Algebraic Methodology and Software Technology
Formal Verification of Descriptions with Distinct Order of Memory Operations
ASIAN '99 Proceedings of the 5th Asian Computing Science Conference on Advances in Computing Science
Generalized Symbolic Trajectory Evaluation - Abstraction in Action
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Formal Verification of Designs with Complex Control by Symbolic Simulation
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Vacuity Detection in Temporal Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Framework for Microprocessor Correctness Statements
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
A Practical Approach to Coverage in Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Practical concurrent ASIC and system design and verification
EDTC '97 Proceedings of the 1997 European conference on Design and Test
WIFT '95 Proceedings of the 1st Workshop on Industrial-Strength Formal Specification Techniques
Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Introduction to generalized symbolic trajectory evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Symbolic Techniques in Satisfiability Solving
Journal of Automated Reasoning
Coverage metrics for temporal logic model checking
Formal Methods in System Design
Formal Methods in System Design
What causes a system to satisfy a specification?
ACM Transactions on Computational Logic (TOCL)
Formal Methods in System Design
Beyond vacuity: towards the strongest passing formula
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Contradictory antecedent debugging in bounded model checking
Proceedings of the 19th ACM Great Lakes symposium on VLSI
On the notion of vacuous truth
LPAR'07 Proceedings of the 14th international conference on Logic for programming, artificial intelligence and reasoning
Model checking-based genetic programming with an application to mutual exclusion
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
TAP'08 Proceedings of the 2nd international conference on Tests and proofs
Strengthening properties using abstraction refinement
Proceedings of the Conference on Design, Automation and Test in Europe
Robust Vacuity for Branching Temporal Logic
ACM Transactions on Computational Logic (TOCL)
Experimental evaluation of classical automata constructions
LPAR'05 Proceedings of the 12th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Search vs. symbolic techniques in satisfiability solving
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Sanity checks in formal verification
CONCUR'06 Proceedings of the 17th international conference on Concurrency Theory
Towards a notion of unsatisfiable and unrealizable cores for LTL
Science of Computer Programming
Learning from vacuously satisfiable scenario-based specifications
FASE'12 Proceedings of the 15th international conference on Fundamental Approaches to Software Engineering
Temporal antecedent failure: refining vacuity
CONCUR'07 Proceedings of the 18th international conference on Concurrency Theory
Supporting incremental behaviour model elaboration
Computer Science - Research and Development
Supporting incremental behaviour model elaboration
Computer Science - Research and Development
Beyond vacuity: towards the strongest passing formula
Formal Methods in System Design
| Hi-index | 0.00 |