Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient Detection of Vacuity in Temporal Model Checking
Formal Methods in System Design - Special issue on CAV '97
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Vacuity Detection in Temporal Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Exploiting Resolution Proofs to Speed Up LTL Vacuity Detection for BMC
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Easier and More Informative Vacuity Checks
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Formal Methods in System Design
Beyond vacuity: towards the strongest passing formula
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
On the notion of vacuous truth
LPAR'07 Proceedings of the 14th international conference on Logic for programming, artificial intelligence and reasoning
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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Model Checking is an automated formal method for verifying whether a finite-state system satisfies a user-supplied specification. The usefulness of the verification result depends on how well the specification distinguishes intended from non-intended system behavior. Vacuity is a notion that helps formalize this distinction in order to improve the user's understanding of why a property is satisfied. The goal of this paper is to expose vacuity in a property in a way that increases our knowledge of the design. Our approach, based on abstraction refinement, computes a maximal set of atomic subformula occurrences that can be strengthened without compromising satisfaction. The result is a shorter and stronger and thus, generally, more valuable property. We quantify the benefits of our technique on a substantial set of circuit benchmarks.