Logic testing and design for testability
Logic testing and design for testability
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Symbolic guided search for CTL model checking
Proceedings of the 37th Annual Design Automation Conference
Symbolic Model Checking
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Hints to accelerate Symbolic Traversal
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Vacuity Detection in Temporal Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Efficient Decision Procedures for Model Checking of Linear Time Logic Properties
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
A Practical Approach to Coverage in Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Efficient Detection of Vacuity in ACTL Formulas
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Dos and don'ts of CTL state coverage estimation
Proceedings of the 40th annual Design Automation Conference
Coverage metrics for requirements-based testing
Proceedings of the 2006 international symposium on Software testing and analysis
Coverage metrics for temporal logic model checking
Formal Methods in System Design
Safety and Software Intensive Systems: Challenges Old and New
FOSE '07 2007 Future of Software Engineering
Properties Incompleteness Evaluation by Functional Verification
IEEE Transactions on Computers
What causes a system to satisfy a specification?
ACM Transactions on Computational Logic (TOCL)
Requirements Coverage as an Adequacy Measure for Conformance Testing
ICFEM '08 Proceedings of the 10th International Conference on Formal Methods and Software Engineering
Formal Methods in System Design
Contradictory antecedent debugging in bounded model checking
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A formal analysis of requirements-based testing
Proceedings of the eighteenth international symposium on Software testing and analysis
Complementary Criteria for Testing Temporal Logic Properties
TAP '09 Proceedings of the 3rd International Conference on Tests and Proofs
The role of mutation analysis for property qualification
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Finding environment guarantees
FASE'07 Proceedings of the 10th international conference on Fundamental approaches to software engineering
Proceedings of the 14th international SPIN conference on Model checking software
On the notion of vacuous truth
LPAR'07 Proceedings of the 14th international conference on Logic for programming, artificial intelligence and reasoning
Property analysis and design understanding
Proceedings of the Conference on Design, Automation and Test in Europe
Strengthening properties using abstraction refinement
Proceedings of the Conference on Design, Automation and Test in Europe
Robust Vacuity for Branching Temporal Logic
ACM Transactions on Computational Logic (TOCL)
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Sanity checks in formal verification
CONCUR'06 Proceedings of the 17th international conference on Concurrency Theory
Whodunit? causal analysis for counterexamples
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Towards a notion of unsatisfiable and unrealizable cores for LTL
Science of Computer Programming
Survey: Linear Temporal Logic Symbolic Model Checking
Computer Science Review
Patterns for a log-based strengthening of declarative compliance models
IFM'12 Proceedings of the 9th international conference on Integrated Formal Methods
Temporal antecedent failure: refining vacuity
CONCUR'07 Proceedings of the 18th international conference on Concurrency Theory
Beyond vacuity: towards the strongest passing formula
Formal Methods in System Design
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Vacuity detection in model checking looks for properties that hold in a model, and can be strengthened without causing them to fail. Such properties often signal problems in the model, its environment, or the properties themselves. The seminal paper of Beer et al. [1] proposed an efficient algorithm applicable to a restricted set of properties. Subsequently, Kupferman and Vardi [15] extended vacuity detection to more expressive specification mechanisms. They advocated a more minute examination of temporal logic formulae than the one adopted in [1]. However, they did not address the issues of practicality and usefulness of this more scrupulous inspection. In this paper we discuss efficient algorithms for the detection of vacuous passes of temporal logic formulae, showing that a thorough vacuity check for CTL formulae can be carried out with very small overhead, and even, occasionally, in less time than plain model checking. We also demonstrate the usefulness of such a careful analysis with the help of case studies.