Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification of pipeline control using controlled token nets and abstract interpretation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Symbolic Model Checking
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Improvements in Coverability Analysis
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
A Practical Approach to Coverage in Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Dos and don'ts of CTL state coverage estimation
Proceedings of the 40th annual Design Automation Conference
Property-Specific Testbench Generation for Guided Simulation
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Improving simulation-based verification by means of formal methods
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
An empirical framework for comparing effectiveness of testing and property-based formal analysis
PASTE '05 Proceedings of the 6th ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering
Formal verification coverage: computing the coverage gap between temporal specifications
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Transition-based coverage estimation for symbolic model checking
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Word level functional coverage computation
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Tightly integrate dynamic verification with formal verification: a GSTE based approach
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Coverage metrics for temporal logic model checking
Formal Methods in System Design
BUSpec: A framework for generation of verification aids for standard bus protocol specifications
Integration, the VLSI Journal
Design by Contract to Improve Software Vigilance
IEEE Transactions on Software Engineering
Properties Incompleteness Evaluation by Functional Verification
IEEE Transactions on Computers
Incremental ABV for functional validation of TL-to-RTL design refinement
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Estimating functional coverage in bounded model checking
Proceedings of the conference on Design, automation and test in Europe
Verification-guided soft error resilience
Proceedings of the conference on Design, automation and test in Europe
Too Few or Too Many Properties? Measure it by ATPG!
Journal of Electronic Testing: Theory and Applications
What causes a system to satisfy a specification?
ACM Transactions on Computational Logic (TOCL)
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Symbolic counter-example generation for model checking
AEE'08 Proceedings of the 7th WSEAS International Conference on Application of Electrical Engineering
Design intent coverage revisited
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal Methods in System Design
A theory of mutations with applications to vacuity, coverage, and fault tolerance
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
A Framework for Inherent Vacuity
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
The role of mutation analysis for property qualification
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
TAP'08 Proceedings of the 2nd international conference on Tests and proofs
Coverage in interpolation-based model checking
Proceedings of the 47th Design Automation Conference
Debugging unrealizable specifications with model-based diagnosis
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Checking models, proving programs, and testing systems
TAP'11 Proceedings of the 5th international conference on Tests and proofs
Using coverage to deploy formal verification in a simulation world
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
CASSIS'04 Proceedings of the 2004 international conference on Construction and Analysis of Safe, Secure, and Interoperable Smart Devices
Incremental formal verification of hardware
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Sanity checks in formal verification
CONCUR'06 Proceedings of the 17th international conference on Concurrency Theory
Hardware design and simulation for verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Improving testbench evaluation using normalized formal properties
VECoS'09 Proceedings of the Third international conference on Verification and Evaluation of Computer and Communication Systems
Cohesive Coverage Management: Simulation Meets Formal Methods
Journal of Electronic Testing: Theory and Applications
A guiding coverage metric for formal verification
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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