The complexity of propositional linear temporal logics
Journal of the ACM (JACM)
The complementation problem for Bu¨chi automata with applications to temporal logic
Theoretical Computer Science
On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Reasoning about infinite computations
Information and Computation
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Efficient Detection of Vacuity in Temporal Model Checking
Formal Methods in System Design - Special issue on CAV '97
Model Checking of Safety Properties
Formal Methods in System Design
Vacuity Checking in the Modal Mu-Calculus
AMAST '02 Proceedings of the 9th International Conference on Algebraic Methodology and Software Technology
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Debugging temporal specifications with concept analysis
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
A Coverage Analysis for Safety Property Lists
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
A Quantitative Completeness Analysis for Property-Sets
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Easier and More Informative Vacuity Checks
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
ICALP '08 Proceedings of the 35th international colloquium on Automata, Languages and Programming, Part II
Anzu: a tool for property synthesis
CAV'07 Proceedings of the 19th international conference on Computer aided verification
RAT: a tool for the formal analysis of requirements
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Finding state solutions to temporal logic queries
IFM'07 Proceedings of the 6th international conference on Integrated formal methods
Proceedings of the 14th international SPIN conference on Model checking software
On the notion of vacuous truth
LPAR'07 Proceedings of the 14th international conference on Logic for programming, artificial intelligence and reasoning
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Sanity checks in formal verification
CONCUR'06 Proceedings of the 17th international conference on Concurrency Theory
Temporal antecedent failure: refining vacuity
CONCUR'07 Proceedings of the 18th international conference on Concurrency Theory
Debugging unrealizable specifications with model-based diagnosis
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
A multi-encoding approach for LTL symbolic satisfiability checking
FM'11 Proceedings of the 17th international conference on Formal methods
Evaluating LTL satisfiability solvers
ATVA'11 Proceedings of the 9th international conference on Automated technology for verification and analysis
Towards a notion of unsatisfiable cores for LTL
FSEN'09 Proceedings of the Third IPM international conference on Fundamentals of Software Engineering
Towards a notion of unsatisfiable and unrealizable cores for LTL
Science of Computer Programming
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
Propositional temporal proving with reductions to a SAT problem
CADE'13 Proceedings of the 24th international conference on Automated Deduction
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
Behavioral diagnosis of LTL specifications at operator level
IJCAI'13 Proceedings of the Twenty-Third international joint conference on Artificial Intelligence
Beyond vacuity: towards the strongest passing formula
Formal Methods in System Design
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Vacuity checking is traditionally performed after model checking has terminated successfully. It ensures that all the elements of the specification have played a role in its satisfaction by the design. Vacuity checking gets as input both design and specification, and is based on an in-depth investigation of the relation between them. Vacuity checking has been proven to be very useful in detecting errors in the modeling of the design or the specification. The need to check the quality of specifications is even more acute in property-based design , where the specification is the only input, serving as a basis to the development of the system. Current work on property assurance suggests various sanity checks, mostly based on satisfiability, non-validity, and realizability, but lacks a general framework for reasoning about the quality of specifications. We describe a framework for inherent vacuity , which carries the theory of vacuity in model checking to the setting of property-based design. Essentially, a specification is inherently vacuous if it can be mutated into a simpler equivalent specification, which we show to coincide with the fact the specification is satisfied vacuously in all systems. We also study the complexity of detecting inherent vacuity, and conclude that while inherent vacuity leads to specifications that better capture designer intent, it is not more complex than simple property-assurance checks.