A Structure-preserving Clause Form Translation
Journal of Symbolic Computation
On the synthesis of a reactive module
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
ACM Transactions on Computational Logic (TOCL)
Efficient Detection of Vacuity in Temporal Model Checking
Formal Methods in System Design - Special issue on CAV '97
Another Look at LTL Model Checking
Formal Methods in System Design
Simple on-the-fly automatic verification of linear temporal logic
Proceedings of the Fifteenth IFIP WG6.1 International Symposium on Protocol Specification, Testing and Verification XV
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
From Falsification to Verification
FST TCS '01 Proceedings of the 21st Conference on Foundations of Software Technology and Theoretical Computer Science
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Verification of Proofs of Unsatisfiability for CNF Formulas
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Formal analysis of hardware requirements
Proceedings of the 43rd annual Design Automation Conference
Coverage metrics for temporal logic model checking
Formal Methods in System Design
Exploiting Resolution Proofs to Speed Up LTL Vacuity Detection for BMC
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Easier and More Informative Vacuity Checks
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
Principles of Model Checking (Representation and Mind Series)
Principles of Model Checking (Representation and Mind Series)
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Finding Minimal Unsatisfiable Cores of Declarative Specifications
FM '08 Proceedings of the 15th international symposium on Formal Methods
Beyond vacuity: towards the strongest passing formula
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
A Framework for Inherent Vacuity
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
From Informal Requirements to Property-Driven Formal Validation
Formal Methods for Industrial Critical Systems
Diagnosing and solving over-determined constraint satisfaction problems
IJCAI'93 Proceedings of the 13th international joint conference on Artifical intelligence - Volume 1
The LPSAT engine & its application to resource planning
IJCAI'99 Proceedings of the 16th international joint conference on Artifical intelligence - Volume 1
Non-standard reasoning services for the debugging of description logic terminologies
IJCAI'03 Proceedings of the 18th international joint conference on Artificial intelligence
A resolution method for temporal logic
IJCAI'91 Proceedings of the 12th international joint conference on Artificial intelligence - Volume 1
A simple and flexible way of computing small unsatisfiable cores in SAT modulo theories
SAT'07 Proceedings of the 10th international conference on Theory and applications of satisfiability testing
RAT: a tool for the formal analysis of requirements
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Boolean abstraction for temporal logic satisfiability
CAV'07 Proceedings of the 19th international conference on Computer aided verification
MUST: provide a finer-grained explanation of unsatisfiability
CP'07 Proceedings of the 13th international conference on Principles and practice of constraint programming
On the notion of vacuous truth
LPAR'07 Proceedings of the 14th international conference on Logic for programming, artificial intelligence and reasoning
Diagnostic information for realizability
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
Debugging OWL-DL ontologies: a heuristic approach
ISWC'05 Proceedings of the 4th international conference on The Semantic Web
Incremental and complete bounded model checking for full PLTL
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
A scalable algorithm for minimal unsatisfiable core extraction
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
Minimally unsatisfiable boolean circuits
SAT'11 Proceedings of the 14th international conference on Theory and application of satisfiability testing
Analyzing unsynthesizable specifications for high-level robot behavior using LTLMoP
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Towards a notion of unsatisfiable and unrealizable cores for LTL
Science of Computer Programming
SMT-based scenario verification for hybrid systems
Formal Methods in System Design
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Unsatisfiable cores, i.e., parts of an unsatisfiable formula that are themselves unsatisfiable, have important uses in debugging specifications, speeding up search in model checking or SMT, and generating certificates of unsatisfiability. While unsatisfiable cores have been well investigated for Boolean SAT and constraint programming, the notion of unsatisfiable cores for temporal logics such as LTL has not received much attention. In this paper we investigate notions of unsatisfiable cores for LTL that arise from the syntax tree of an LTL formula, from converting it into a conjunctive normal form, and from proofs of its unsatisfiability. The resulting notions are more fine-granular than existing ones.