On Approaches to Explaining Infeasibility of Sets of Boolean Clauses
ICTAI '08 Proceedings of the 2008 20th IEEE International Conference on Tools with Artificial Intelligence - Volume 01
Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts
Proceedings of the 46th Annual Design Automation Conference
Minimal Unsatisfiability: Models, Algorithms and Applications (Invited Paper)
ISMVL '10 Proceedings of the 2010 40th IEEE International Symposium on Multiple-Valued Logic
Boosting minimal unsatisfiable core extraction
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
On improving MUS extraction algorithms
SAT'11 Proceedings of the 14th international conference on Theory and application of satisfiability testing
Towards a notion of unsatisfiable cores for LTL
FSEN'09 Proceedings of the Third IPM international conference on Fundamentals of Software Engineering
Towards efficient MUS extraction
AI Communications - 18th RCRA International Workshop on “Experimental evaluation of algorithms for solving problems with combinatorial explosion”
On efficient computation of variable MUSes
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
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Automated reasoning tasks in many real-world domains involve analysis of redundancies in unsatisfiable instances of SAT. In CNF-based instances, some of the redundancies can be captured by computing a minimally unsatisfiable subset of clauses (MUS). However, the notion of MUS does not apply directly to non-clausal instances of SAT, particularly those that are represented as Boolean circuits. In this paper we identify certain types of redundancies in unsatisfiable Boolean circuits, and propose a number of algorithms to compute minimally unsatisfiable, that is, irredundant, subcircuits.