Reasoning about infinite computations
Information and Computation
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient Detection of Vacuity in Temporal Model Checking
Formal Methods in System Design - Special issue on CAV '97
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
An Algorithmic Approach to Design Exploration
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
NIMBUS: A Tool for Specification Centered Development
RE '03 Proceedings of the 11th IEEE International Conference on Requirements Engineering
Specifying and analyzing early requirements in Tropos
Requirements Engineering
Incremental and complete bounded model checking for full PLTL
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Interactive presentation: Automatic hardware synthesis from specifications: a case study
Proceedings of the conference on Design, automation and test in Europe
Specify, Compile, Run: Hardware from PSL
Electronic Notes in Theoretical Computer Science (ENTCS)
Requirements Validation for Hybrid Systems
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
The COMPASS Approach: Correctness, Modelling and Performability of Aerospace Systems
SAFECOMP '09 Proceedings of the 28th International Conference on Computer Safety, Reliability, and Security
Codesign of dependable systems: a component-based modeling language
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
RAT: a tool for the formal analysis of requirements
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Boolean abstraction for temporal logic satisfiability
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Automated analysis of compositional multi-agent systems
International Journal of Agent-Oriented Software Engineering
Diagnostic information for realizability
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
Debugging unrealizable specifications with model-based diagnosis
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
A multi-encoding approach for LTL symbolic satisfiability checking
FM'11 Proceedings of the 17th international conference on Formal methods
Evaluating LTL satisfiability solvers
ATVA'11 Proceedings of the 9th international conference on Automated technology for verification and analysis
Towards a notion of unsatisfiable cores for LTL
FSEN'09 Proceedings of the Third IPM international conference on Fundamentals of Software Engineering
Synthesis of Reactive(1) designs
Journal of Computer and System Sciences
Towards a notion of unsatisfiable and unrealizable cores for LTL
Science of Computer Programming
Validation of requirements for hybrid systems: A formal approach
ACM Transactions on Software Engineering and Methodology (TOSEM)
Synthesis from incompatible specifications
Proceedings of the tenth ACM international conference on Embedded software
Behavioral diagnosis of LTL specifications at operator level
IJCAI'13 Proceedings of the Twenty-Third international joint conference on Artificial Intelligence
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Formal languages are increasingly used to describe the functional requirements (specifications) of circuits. These requirements are used as a means to communicate design intent and as basis for verification. In both settings it is of utmost importance that the specifications are of high quality. However, formal requirements are seldom the object of validation, even though they can be hard to understand and interactions between them can be subtle. In this paper we present techniques and guidelines to explore and assure the quality of a formal specification. We define a technique to interactively explore the semantics of a specification by simulating its behavior for user-defined scenarios. Further-more, we define techniques to automatically check specifications against a set of user-provided assertions, which must be satisfied, and a set of possibilities, which must not be conradicted. The proposed techniques support the user in the iterative development and refinement of high-quality specifications.