Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Model checking, abstraction, and compositional verification
Model checking, abstraction, and compositional verification
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification of an IBM CoreConnect processor local bus arbiter core
Proceedings of the 37th Annual Design Automation Conference
A methodology for hardware verification using compositional model checking
Science of Computer Programming - Special issue on mathematics of program construction
Symbolic Model Checking
Timing Diagrams: Formalization and Algorithmic Verification
Journal of Logic, Language and Information
The Formal Design of 1M-gate ASICs
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Temporal Debugging for Concurrent Systems
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Hints to accelerate Symbolic Traversal
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Efficient Debugging in a Formal Verification Environment
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
On-the-Fly Model Checking of RCTL Formulas
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
An Abstraction Algorithm for the Verification of Generalized C-Slow Designs
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Model Checking Synchronous Timing Diagrams
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Source-Level Transformations for Improved Formal Verification
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Formal analysis of hardware requirements
Proceedings of the 43rd annual Design Automation Conference
Planned and traversable play-out: a flexible method for executing scenario-based programs
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
A framework for counterexample generation and exploration
FASE'05 Proceedings of the 8th international conference, held as part of the joint European Conference on Theory and Practice of Software conference on Fundamental Approaches to Software Engineering
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In recent years, the technique of symbolic model checking has proven itself to be extremely useful in the verification of hardware. However, after almost a decade, the use of model checking techniques is still considered complicated, and is mostly practiced by experts. In this paper we address the question of how model checking techniques can be made more accessible to the hardware designer community. We introduce the concept of exploration through model checking, and demonstrate how, when differently tuned, the known techniques can be used to easily obtain interesting traces out of the model, rather than used for the discovery of hard-to-find bugs. We present a set of algorithms, which support the exploration flavor of model checking.