Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Verifying the performance of the PCI local bus using symbolic techniques
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
RuleBase: Model Checking at IBM
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Verification of the Futurebus+ Cache Coherence Protocol
Verification of the Futurebus+ Cache Coherence Protocol
Formal Methods in System Design
An Algorithmic Approach to Design Exploration
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
A Theory of Consistency for Modular Synchronous Systems
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Memory arbiter synthesis and verification for a radar memory interface card
Nordic Journal of Computing
Directed-simulation assisted formal verification of serial protocol and bridge
Proceedings of the 43rd annual Design Automation Conference
Formal performance evaluation of AMBA-based system-on-chip designs
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
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Integration, the VLSI Journal
Formal verification of a pervasive interconnect bus system in a high-performance microprocessor
Proceedings of the conference on Design, automation and test in Europe
Multi-core design automation challenges
Proceedings of the 44th annual Design Automation Conference
Verification of AMBA Using a Combination of Model Checking and Theorem Proving
Electronic Notes in Theoretical Computer Science (ENTCS)
A Trojan-resistant system-on-chip bus architecture
MILCOM'09 Proceedings of the 28th IEEE conference on Military communications
Formal modeling and model checking analysis of the wishbone system-on-chip bus protocol
ICICA'12 Proceedings of the Third international conference on Information Computing and Applications
Automated determination of top level control signals
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper describes the model checking effort for an arbiter core for the IBM CoreConnect Architecture. We present our verification methodology and describe how it was influenced by the architecture. We also present and analyze the bugs found and discuss the difficulties associated with verifying complex on-chip buses, highlighting the need for better tools and methodologies for their specification and verification.