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The target system of this paper is a radar memory interface card described in the IST AMETIST project. We present a way to synthesise and verify a memory arbiter for the interface card by specifying two different problems of logic model checking. In the process, we minimise the amount of memory used for intermediate buffering of data streams by augmenting the model with cost variables and applying a guided model checker -- Uppaal CORA. It is verified that the resultant arbiter does not deadlock and never starves nor overflows any of the buffers. The model is constructed as an abstraction of the behaviour of the system from the point of view of memory communication. The key factors to the success of the synthesis task are the rather simple abstract model and the application of bit-state hashing for speeding up reachability. It is suggested that a method of sweeping over a range of hash table sizes for to enhance the performance of reachability would a practical improvement for solving synthesis tasks.