Communication and concurrency
Design and validation of computer protocols
Design and validation of computer protocols
The existence of refinement mappings
Theoretical Computer Science
Theoretical Computer Science
Automatic verification of real-time communicating systems by constraint-solving
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
Model Checking of Real-Time Reachability Properties Using Abstractions
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Verification of an Audio Protocol with Bus Collision Using UPPAAL
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Scheduling a Steel Plant with Timed Automata
RTCSA '99 Proceedings of the Sixth International Conference on Real-Time Computing Systems and Applications
Compositional and symbolic model-checking of real-time systems
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Efficient verification of real-time systems: compact data structure and state-space reduction
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Timed Automata with Asynchronous Processes: Schedulability and Decidability
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Optimal scheduling using priced timed automata
ACM SIGMETRICS Performance Evaluation Review
A generic approach to schedulability analysis of real-time tasks
Nordic Journal of Computing
Memory arbiter synthesis and verification for a radar memory interface card
Nordic Journal of Computing
Schedulability analysis of fixed-priority systems using timed automata
Theoretical Computer Science - Tools and algorithms for the construction and analysis of systems (TACAS 2003)
Predictable real-time software synthesis
Real-Time Systems
Task automata: Schedulability, decidability and undecidability
Information and Computation
Schedulability analysis using two clocks
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
A novel SAT-based approach to the task graph cost-optimal scheduling problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Priced timed automata: algorithms and applications
FMCO'04 Proceedings of the Third international conference on Formal Methods for Components and Objects
Verification, performance analysis and controller synthesis for real-time systems
FSEN'09 Proceedings of the Third IPM international conference on Fundamentals of Software Engineering
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In this paper we address the problem of scheduling and synthesizing distributed control programs for a batch production plant. We use a timed automata model of the batch plant and the verification tool UPPAAL to solve the scheduling problem.In modeling the plant, we aim at a level of abstraction which is sufficiently accurate in order that synthesis of control programs from generated timed traces is possible. Consequently, the models quickly become too detailed and complicated for immediate automatic synthesis. In fact, only models of plants producing two batches can be analyzed directly! To overcome this problem, we present a general method allowing the user to guide the model-checker according to heuristically chosen strategies. The guidance is specified by augmenting the model with additional guidance variables and by decorating transitions with extra guards on these. Applying this method have made synthesis of control programs feasible for a plant producing as many as 60 batches.The synthesized control programs have been executed in a physical plant. Besides proving useful in validating the plant model and in finding some modeling errors, we view this final step as the ultimate litmus test of our methodology's ability to generate executable (and executing) code from basic plant models.