Formal verification of an IBM CoreConnect processor local bus arbiter core
Proceedings of the 37th Annual Design Automation Conference
Formal Design of Cache Memory Protocols in IBM
Formal Methods in System Design
Mambo: a full system simulator for the PowerPC architecture
ACM SIGMETRICS Performance Evaluation Review - Special issue on tools for computer architecture research
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
POWER5 System microarchitecture
IBM Journal of Research and Development - POWER5 and packaging
Reducing Verification Complexity of a Multicore Coherence Protocol Using Assume/Guarantee
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
POWER4 system microarchitecture
IBM Journal of Research and Development
Analog parallelism in ring-based VCOs
Proceedings of the 45th annual Design Automation Conference
Thermal optimization in multi-granularity multi-core floorplanning
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploring concurrency using the parallel analysis tool
Proceedings of the 43rd ACM technical symposium on Computer Science Education
| Hi-index | 0.00 |
The trend to multi-core chip designs presents new challenges for design automation, while the increased reuse of components may offer solutions. This paper describes some of the key challenges with attention paid to three enablers: a physical architecture to streamline chip integration, the linking of early analysis tools around shared data and an updated verification approach for multi-core designs.