The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Microarchitecture evaluation with physical planning
Proceedings of the 40th annual Design Automation Conference
Profile-guided microarchitectural floorplanning for deep submicron processor design
Proceedings of the 41st annual Design Automation Conference
Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects
Proceedings of the 41st annual Design Automation Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Microarchitecture-aware floorplanning using a statistical design of experiments approach
Proceedings of the 42nd annual Design Automation Conference
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Physical aware frequency selection for dynamic thermal management in multi-core systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Multi-core design automation challenges
Proceedings of the 44th annual Design Automation Conference
Bus-aware microarchitectural floorplanning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Understanding the Thermal Implications of Multi-Core Architectures
IEEE Transactions on Parallel and Distributed Systems
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Floorplanning for low power IC design considering temperature variations
Microelectronics Journal
Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
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Multi-core microarchitectures require a careful balance between many competing objectives to achieve the highest possible performance. Integrated Early Analysis is the consideration of all of these factors at an early stage. Toward this goal, this work presents the first adaptive multi-granularity multi-core microarchitecture-level floorplanner that simultaneously optimizes temperature and performance, and considers memory bus length. We include simultaneous optimization at both the module-level and the core/cache-bank level. Related experiments show that our methodology is effective for optimizing multi-core architectures.