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A generic architecture for on-chip packet-switched interconnections
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Route packets, not wires: on-chip inteconnection networks
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Communication Architectures for System-on-Chip
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Efficient Synthesis of Networks On Chip
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×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
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DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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Proceedings of the conference on Design, automation and test in Europe: Proceedings
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A topology design customization approach for STNoC
Proceedings of the 2nd international conference on Nano-Networks
Thermal optimization in multi-granularity multi-core floorplanning
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Graph-based methods for the analysis of large-scale multiagent systems
Proceedings of The 8th International Conference on Autonomous Agents and Multiagent Systems - Volume 1
Custom networks-on-chip architectures with multicast routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Moths: Mobile threads for on-chip networks
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Journal of Systems Architecture: the EUROMICRO Journal
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In this paper, we present a methodology for customized communication architecture synthesis that matches the communication requirements of the target application. This is an important problem, particularly for network-based implementations of complex applications. Our approach is based on using frequently encountered generic communication primitives as an alphabet capable of characterizing any given communication pattern. The proposed algorithm searches through the entire design space for a solution that minimizes the system total energy consumption, while satisfying the other design constraints. Compared to the standard mesh architecture, the customized architecture generated by the newly proposed approach shows about 36% throughput increase and 51% reduction in the energy required to encrypt 128 bits of data with a standard encryption algorithm.