A generic architecture for on-chip packet-switched interconnections

Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

A practical tool box for system level communication synthesis

Proceedings of the ninth international symposium on Hardware/software codesign

Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip

Proceedings of the 38th annual Design Automation Conference

Powering networks on chips: energy-efficient and reliable interconnect design for SoCs

Proceedings of the 14th international symposium on Systems synthesis

Networks on Chips: A New SoC Paradigm

Computer

A Scalable High-Performance Computing Solution for Networks on Chips

IEEE Micro

System level interconnect design for network-on-chip using interconnect IPs

Proceedings of the 2003 international workshop on System-level interconnect prediction

Extending Platform-Based Design to Network on Chip Systems

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

Interfacing Cores with On-chip Packet-Switched Networks

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

Will networks on chip close the productivity gap?

Networks on chip

Guaranteeing the quality of services in networks on chip

Networks on chip

On packet switched networks for on-chip communication

Networks on chip

A parallel computer as a NOC region

Networks on chip

An IP-based on-chip packet-switched network

Networks on chip

Multi-level software validation for NOC

Networks on chip

A modular simulation framework for architectural exploration of on-chip interconnection networks

Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Network-on-Chip Modeling for System-Level Multiprocessor Simulation

RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium

Optical solutions for system-level interconnect

Proceedings of the 2004 international workshop on System level interconnect prediction

A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoCs

Proceedings of the conference on Design, automation and test in Europe - Volume 2

An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration

Proceedings of the conference on Design, automation and test in Europe - Volume 2

Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip

Proceedings of the conference on Design, automation and test in Europe - Volume 2

Bandwidth-Constrained Mapping of Cores onto NoC Architectures

Proceedings of the conference on Design, automation and test in Europe - Volume 2

×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip

Proceedings of the conference on Design, automation and test in Europe - Volume 2

OCCN: A Network-On-Chip Modeling and Simulation Framework

Proceedings of the conference on Design, automation and test in Europe - Volume 3

RASoC: A Router Soft-Core for Networks-on-Chip

Proceedings of the conference on Design, automation and test in Europe - Volume 3

Interconnect intellectual property for network-on-chip (NoC)

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip

Packetization and routing analysis of on-chip multiprocessor networks

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip

QNoC: QoS architecture and design process for network on chip

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip

OCCN: a NoC modeling framework for design exploration

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip

Managing power consumption in networks on chips

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

FIFO power optimization for on-chip networks

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Reliable communication in systems on chips

Proceedings of the 41st annual Design Automation Conference

Operating-system controlled network on chip

Proceedings of the 41st annual Design Automation Conference

SUNMAP: a tool for automatic topology selection and generation for NoCs

Proceedings of the 41st annual Design Automation Conference

Reducing test time with processor reuse in network-on-chip based systems

SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design

ParIS: a parameterizable interconnect switch for networks-on-chip

SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design

Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Micro-Network for SoC: Implementation of a 32-Port SPIN network

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Network Processing Challenges and an Experimental NPU Platform

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2

SPIN: A Scalable, Packet Switched, On-Chip Micro-Network

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2

Reusing an on-chip network for the test of core-based systems

ACM Transactions on Design Automation of Electronic Systems (TODAES)

NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip

IEEE Transactions on Parallel and Distributed Systems

Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

An Application-Specific Design Methodology for STbus Crossbar Generation

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

MultiNoC: A Multiprocessing System Enabled by a Network on Chip

Proceedings of the conference on Design, Automation and Test in Europe - Volume 3

Cost considerations in network on chip

Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics

HERMES: an infrastructure for low area overhead packet-switching networks on chip

Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics

Issues in the development of a practical NoC: the Proteo concept

Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics

Run-time support for heterogeneous multitasking on reconfigurable SoCs

Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics

Quality-of-service and error control techniques for mesh-based network-on-chip architectures

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI

A robust self-calibrating transmission scheme for on-chip networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A low latency router supporting adaptivity for on-chip interconnects

Proceedings of the 42nd annual Design Automation Conference

A Scalable Parallel SoC Architecture for Network Processors

ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures

IEEE Transactions on Computers

Virtual channels in networks on chip: implementation and evaluation on hermes NoC

SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design

Traffic generation and performance evaluation for mesh-based NoCs

SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design

Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Analysis of Error Recovery Schemes for Networks on Chips

IEEE Design & Test

An event-based monitoring service for networks on chip

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Mapping and configuration methods for multi-use-case networks on chips

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Energy-aware mapping for tile-based NoC architectures under performance constraints

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Core Network Interface Architecture and Latency Constrained On-Chip Communication

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

Deadlock-free routing and component placement for irregular mesh-based networks-on-chip

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

GALS networks on chip: a new solution for asynchronous delay-insensitive links

Proceedings of the conference on Design, automation and test in Europe: Designers' forum

Efficient link capacity and QoS design for network-on-chip

Proceedings of the conference on Design, automation and test in Europe: Proceedings

A methodology for mapping multiple use-cases onto networks on chips

Proceedings of the conference on Design, automation and test in Europe: Proceedings

A survey of research and practices of Network-on-chip

ACM Computing Surveys (CSUR)

HIBI Communication Network for System-on-Chip

Journal of VLSI Signal Processing Systems

Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems

Proceedings of the 43rd annual Design Automation Conference

A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip

Proceedings of the 43rd annual Design Automation Conference

Bounded arbitration algorithm for QoS-supported on-chip communication

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

Automatic phase detection for stochastic on-chip traffic generation

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

A Simple Data Transfer Technique Using Local Address for Networks-on-Chips

IEEE Transactions on Parallel and Distributed Systems

ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture

On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect

The psi-cube: a bus-based cube-type clustering network for high-performance on-chip systems

Parallel Computing

A buffered crossbar-based chip interconnection framework supporting quality of service

Proceedings of the 17th ACM Great Lakes symposium on VLSI

Efficient space-time noc path allocation based on mutual exclusion and pre-reservation

Proceedings of the 17th ACM Great Lakes symposium on VLSI

Performances improvement of FPGA using novel multilevel hierarchical interconnection structure

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Physical design of the VCI wrappers for the on-chip packet-switched network named SPIN

Computers and Electrical Engineering

Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms

Computers and Electrical Engineering

On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip

Transaction-Based Communication-Centric Debug

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip

The Power of Priority: NoC Based Distributed Cache Coherency

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip

NoC-Based FPGA: Architecture and Routing

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip

Implementing DSP Algorithms with On-Chip Networks

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip

Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture

Proceedings of the conference on Design, automation and test in Europe

A robust protocol for concurrent on-line test (COLT) of NoC-based systems-on-a-chip

Proceedings of the 44th annual Design Automation Conference

SAPP: scalable and adaptable peak power management in nocs

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design

Buffer sizing for QoS flows in wormhole packet switching NoCs

Proceedings of the 20th annual conference on Integrated circuits and systems design

Fitting the router characteristics in NoCs to meet QoS requirements

Proceedings of the 20th annual conference on Integrated circuits and systems design

A tool for automatic detection of deadlock in wormhole networks on chip

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Analysis and optimization of prediction-based flow control in networks-on-chip

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Bringing NoCs to 65 nm

IEEE Micro

Arbiter synthesis approach for SoC multi-processor systems

Computers and Electrical Engineering

Power and reliability management of SoCs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Run-time adaptive on-chip communication scheme

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Trends toward on-chip networked microsystems

International Journal of High Performance Computing and Networking

Lossless static vs. dynamic reconfiguration of interconnection networks in parallel and distributed computer systems

Proceedings of the 2007 Summer Computer Simulation Conference

Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology

Proceedings of the 18th ACM Great Lakes symposium on VLSI

Mesh-of-tree deterministic routing for network-on-chip architecture

Proceedings of the 18th ACM Great Lakes symposium on VLSI

MLMIN: A multicore processor and parallel computer network topology for multicast

Computers and Operations Research

Designing efficient irregular networks for heterogeneous systems-on-chip

Journal of Systems Architecture: the EUROMICRO Journal

A monitoring-aware network-on-chip design flow

Journal of Systems Architecture: the EUROMICRO Journal

Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip

Journal of Systems Architecture: the EUROMICRO Journal

Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions

Journal of Systems Architecture: the EUROMICRO Journal

Chip Multiprocessor Traffic Models Providing Consistent Multicast and Spatial Distributions

Simulation

QoS-supported on-chip communication for multi-processors

International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems

Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip

Statistical Approach to NoC Design

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip

Multicast parallel pipeline router architecture for network-on-chip

Proceedings of the conference on Design, automation and test in Europe

ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip

CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis

Relieving physical issues in new NoC-based SoCs

Proceedings of the 2nd international conference on Nano-Networks

QNoC asynchronous router

Integration, the VLSI Journal

CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs

Microprocessors & Microsystems

Long-range dependence and on-chip processor traffic

Microprocessors & Microsystems

Synthesis of networks on chips for 3D systems on chips

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Robust concurrent online testing of network-on-chip-based SoCs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time

IEICE - Transactions on Information and Systems

Comparison of network-on-chip topologies for multicore systems considering multicast and local traffic

Proceedings of the 2nd International Conference on Simulation Tools and Techniques

Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Triplet-based topology for on-chip networks

WSEAS Transactions on Computers

Networks-on-chip based on dynamic wormhole packet identity mapping management

VLSI Design

Power optimization for application-specific networks-on-chips: A topology-based approach

Microprocessors & Microsystems

Performance analysis of small non-uniform packet switches

Performance Evaluation

Evaluating the energy consumption and the silicon area of on-chip interconnect architectures

Journal of Systems Architecture: the EUROMICRO Journal

NoC topology synthesis for supporting shutdown of voltage islands in SoCs

Proceedings of the 46th Annual Design Automation Conference

Region-based routing: a mechanism to support efficient routing algorithms in NoCs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures

Computers and Electrical Engineering

An outlook on design technologies for future integrated systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A system-level design methodology for application-specific networks-on-chip

Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics

A method for calculating hard QoS guarantees for Networks-on-Chip

Proceedings of the 2009 International Conference on Computer-Aided Design

Quality-of-service and error control techniques for mesh-based network-on-chip architectures

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI

On a web-graph-based micronetwork architecture for SoCs

International Journal of Computers and Applications

Formal models for multicast traffic in network on chip architectures with compositional high-level Petri nets

ICATPN'07 Proceedings of the 28th international conference on Applications and theory of Petri nets and other models of concurrency

THIN: a new hierarchical interconnection network-on-chip for SOC

ICA3PP'07 Proceedings of the 7th international conference on Algorithms and architectures for parallel processing

A modeling tool for simulating and design of on-chip network systems

Microprocessors & Microsystems

Simulation of a signal arbitration algorithm for a sensor array

EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory

The SKB: a semi-completely-connected bus for on-chip systems

NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing

A novel congestion control scheme for elastic flows in network-on-chip based on sum-rate optimization

ICCSA'07 Proceedings of the 2007 international conference on Computational science and its applications - Volume Part III

Network-on-chip architecture design based on mesh-of-tree deterministic routing topology

International Journal of High Performance Systems Architecture

Communication modeling of multicast in all-port wormhole-routed NoCs

Journal of Systems and Software

Virtual point-to-point connections for NoCs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip

PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design

Journal of Signal Processing Systems

A fuzzy-based power-aware routing algorithm for network on chip

ICACT'10 Proceedings of the 12th international conference on Advanced communication technology

Networks on Chips: from research to products

Proceedings of the 47th Design Automation Conference

Lightweight Transactional Memory systems for NoCs based architectures: Design, implementation and comparison of two policies

Journal of Parallel and Distributed Computing

A fully-asynchronous low-power framework for GALS NoC integration

Proceedings of the Conference on Design, Automation and Test in Europe

Feedback control for providing QoS in NoC based multicores

Proceedings of the Conference on Design, Automation and Test in Europe

Leveraging application-level requirements in the design of a NoC for a 4G SoC: a case study

Proceedings of the Conference on Design, Automation and Test in Europe

SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips

Proceedings of the Conference on Design, Automation and Test in Europe

Priority-based packet communication on a bus-shaped structure for FPGA-systems

Proceedings of the Conference on Design, Automation and Test in Europe

Synthesis of low-overhead configurable source routing tables for network interfaces

Proceedings of the Conference on Design, Automation and Test in Europe

Group-caching for NoC based multicore cache coherent systems

Proceedings of the Conference on Design, Automation and Test in Europe

Design of networks on chips for 3D ICs

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

A framework for designing congestion-aware deterministic routing

Proceedings of the Third International Workshop on Network on Chip Architectures

Sunfloor 3D: a tool for networks on chip topology synthesis for 3-D systems on chips

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

On chip interconnects for multiprocessor turbo decoding architectures

Microprocessors & Microsystems

Power-efficient tree-based multicast support for networks-on-chip

Proceedings of the 16th Asia and South Pacific Design Automation Conference

Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chip

Microprocessors & Microsystems

Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach

Journal of Real-Time Image Processing

An analytical model for Network-on-Chip with finite input buffer

Frontiers of Computer Science in China

3D network-on-chip architectures using homogeneous meshes and heterogeneous floorplans

International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)

Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling

Microelectronics Journal

GNLS: a hybrid on-chip communication architecture for SoC designs

International Journal of High Performance Systems Architecture

Performance evaluation of a wormhole-routed algorithm for irregular mesh NoC interconnect

ICDCN'10 Proceedings of the 11th international conference on Distributed computing and networking

Process variation-aware routing in NoC based multicores

Proceedings of the 48th Design Automation Conference

Capacity optimized NoC for multi-mode SoC

Proceedings of the 48th Design Automation Conference

Asynchronous switching for low-power networks-on-chip

Microelectronics Journal

Throughput aware mapping for network on chip design of h.264 decoder

ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking

Realization of video object plane decoder on on-chip network architecture

ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems

Analyzing the performance of mesh and fat-tree topologies for network on chip design

EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing

Design of an asynchronous switch based on butterfly fat-tree for network-on-chip applications

PCM'05 Proceedings of the 6th Pacific-Rim conference on Advances in Multimedia Information Processing - Volume Part II

A switch wrapper design for SNA on-chip-network

ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture

A practical test scheduling using network-based TAM in network on chip architecture

ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture

A fault tolerant approach to object oriented design and synthesis of embedded systems

LADC'05 Proceedings of the Second Latin-American conference on Dependable Computing

A method for router table compression for application specific routing in mesh topology noc architectures

SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation

A modular simulator framework for network-on-chip based manycore chips using UNISIM

Transactions on High-Performance Embedded Architectures and Compilers IV

The optimum network on chip architectures for video object plane decoder design

ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications

Networks on chips: structure and design methodologies

Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies

A buffer-sizing algorithm for network-on-chips with multiple voltage-frequency Islands

Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies

An efficient routing technique for mesh-of-tree-based NoC and its performance comparison

International Journal of High Performance Systems Architecture

Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router

Microprocessors & Microsystems

Formal verification methodology considerations for network on chips

Proceedings of the International Conference on Advances in Computing, Communications and Informatics

System-level application-specific NoC design for network and multimedia applications

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation

An QoS aware mapping of cores onto NoC architectures

ISPA'07 Proceedings of the 5th international conference on Parallel and Distributed Processing and Applications

Hybrid interconnect design for heterogeneous hardware accelerators

Proceedings of the Conference on Design, Automation and Test in Europe

Virtual networks -- distributed communication resource management

ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)

A network-on-chip-based turbo/LDPC decoder architecture

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe

Using task migration to improve non-contiguous processor allocation in NoC-based CMPs

Journal of Systems Architecture: the EUROMICRO Journal

An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture

Wireless Personal Communications: An International Journal

High-speed dynamic TDMA arbiter for inter-layer communications in 3-D network-on-chip

Journal of High Speed Networks