Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Simulation
IEEE Transactions on Parallel and Distributed Systems
Scalability of Parallel Algorithm-Machine Combinations
IEEE Transactions on Parallel and Distributed Systems
Pausible Clocking: A First Step Toward Heterogeneous Systems
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
A Low-Latency FIFO for Mixed-Clock Systems
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Traffic Configuration for Evaluating Networks on Chips
IWSOC '05 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications
A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
An efficient routing technique for mesh-of-tree-based NoC and its performance comparison
International Journal of High Performance Systems Architecture
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router
Microprocessors & Microsystems
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Network-on-Chip (NoC) is a new paradigm for designing future System-on-Chips (SoCs) where large numbers of Intellectual Property (IP) cores are connected through an interconnection network. The communication between the nodes is achieved by routing packets rather than wires. It supports high degree of reusability, scalability, and parallelism in communication. Here, we present NoC architecture based on Mesh-of-Tree (MoT) deterministic routing. MoT interconnection has the advantage of having small diameter as well as large bisection width. It is known as the fastest network when considered solely in terms of speed. The routing algorithm ensures that the packet will always reach the destination through the shortest path and it is deadlock free. We also present how Globally Asynchronous Locally Synchronous (GALS) style of communication has been implemented by using FIFO in mixed clock system.