Wave pipelining for application-specific networks-on-chips
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Extending Platform-Based Design to Network on Chip Systems
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Interfacing Cores with On-chip Packet-Switched Networks
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Will networks on chip close the productivity gap?
Networks on chip
A design methodology for NOC-based systems
Networks on chip
Guaranteeing the quality of services in networks on chip
Networks on chip
On packet switched networks for on-chip communication
Networks on chip
A parallel computer as a NOC region
Networks on chip
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Network-on-Chip Modeling for System-Level Multiprocessor Simulation
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Proceedings of the 2004 international workshop on System level interconnect prediction
Proceedings of the conference on Design, automation and test in Europe - Volume 1
System Design for DSP Applications Using the MASIC Methodology
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
RASoC: A Router Soft-Core for Networks-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Reconfigurable platforms for ubiquitous computing
Proceedings of the 1st conference on Computing frontiers
Packetization and routing analysis of on-chip multiprocessor networks
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Reliable communication in systems on chips
Proceedings of the 41st annual Design Automation Conference
Operating-system controlled network on chip
Proceedings of the 41st annual Design Automation Conference
System design for DSP applications in transaction level modeling paradigm
Proceedings of the 41st annual Design Automation Conference
ParIS: a parameterizable interconnect switch for networks-on-chip
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
When reconfigurable architecture meets network-on-chip
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Packetized On-Chip Interconnect Communication Analysis for MPSoC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
A Complete Network-On-Chip Emulation Framework
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Application of the object-oriented principles for hardware and embedded system design
Integration, the VLSI Journal
Cost considerations in network on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
LiPaR: A light-weight parallel router for FPGA-based networks-on-chip
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
An event-based monitoring service for networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Application-specific buffer space allocation for networks-on-chip router design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
The routability of multiprocessor network topologies in FPGAs
Proceedings of the 2006 international workshop on System-level interconnect prediction
Improving routing efficiency for network-on-chip through contention-aware input selection
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Deadlock-free routing and component placement for irregular mesh-based networks-on-chip
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Buffer space optimisation with communication synthesis and traffic shaping for NoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
A design methodology for application-specific networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
Formal development of NoC systems in B
Nordic Journal of Computing - Selected papers of the 17th nordic workshop on programming theory (NWPT'05), October 19-21, 2005
A Simple Data Transfer Technique Using Local Address for Networks-on-Chips
IEEE Transactions on Parallel and Distributed Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Resource efficiency of the GigaNetIC chip multiprocessor architecture
Journal of Systems Architecture: the EUROMICRO Journal
A priority assignment strategy of processing elements over an on-chip bus
Proceedings of the 2007 ACM symposium on Applied computing
Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms
Computers and Electrical Engineering
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
The Power of Priority: NoC Based Distributed Cache Coherency
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Implementing DSP Algorithms with On-Chip Networks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Routing table minimization for irregular mesh NoCs
Proceedings of the conference on Design, automation and test in Europe
A robust protocol for concurrent on-line test (COLT) of NoC-based systems-on-a-chip
Proceedings of the 44th annual Design Automation Conference
SAPP: scalable and adaptable peak power management in nocs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Fitting the router characteristics in NoCs to meet QoS requirements
Proceedings of the 20th annual conference on Integrated circuits and systems design
IEEE Micro
Fault-aware communication mapping for NoCs with guaranteed latency
International Journal of Parallel Programming
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power and reliability management of SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DNCOCO'07 Proceedings of the 9th WSEAS International Conference on Data Networks, Communications, Computers
A multiobjective evolutionary algorithm-based optimisation model for network on chip synthesis
International Journal of Innovative Computing and Applications
A new selection policy for adaptive routing in network on chip
EHAC'06 Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Mesh-of-tree deterministic routing for network-on-chip architecture
Proceedings of the 18th ACM Great Lakes symposium on VLSI
MLMIN: A multicore processor and parallel computer network topology for multicast
Computers and Operations Research
Designing efficient irregular networks for heterogeneous systems-on-chip
Journal of Systems Architecture: the EUROMICRO Journal
Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions
Journal of Systems Architecture: the EUROMICRO Journal
Invited paper: Network-on-Chip design and synthesis outlook
Integration, the VLSI Journal
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MOTIM: an industrial application using nocs
Proceedings of the 21st annual symposium on Integrated circuits and system design
A Link-Load Balanced Low Energy Mapping and Routing for NoC
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Link-load balance aware mapping and routing for NoC
WSEAS Transactions on Circuits and Systems
CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs
Microprocessors & Microsystems
Robust concurrent online testing of network-on-chip-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
IEICE - Transactions on Information and Systems
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Routability of network topologies in FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Power optimization for application-specific networks-on-chips: A topology-based approach
Microprocessors & Microsystems
Evaluating the energy consumption and the silicon area of on-chip interconnect architectures
Journal of Systems Architecture: the EUROMICRO Journal
A DP-network for optimal dynamic routing in network-on-chip
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Region-based routing: a mechanism to support efficient routing algorithms in NoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Breaking adaptive multicast deadlock by virtual channel address/data FIFO decoupling
Proceedings of the 2nd International Workshop on Network on Chip Architectures
A networks-on-chip architecture design space exploration - The LIB
Computers and Electrical Engineering
Reliable And Secure Chip Level Communication By Residue Number System Code
Journal of Integrated Design & Process Science
Proceedings of the 6th FPGAworld Conference
Optimal application mapping on NoC infrastructure using NSGA-II and microGA
INES'09 Proceedings of the IEEE 13th international conference on Intelligent Engineering Systems
An analytical performance model for the Spidergon NoC with virtual channels
Journal of Systems Architecture: the EUROMICRO Journal
Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Routing in self-organizing nano-scale irregular networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Predicting the performance of application-specific NoCs implemented on FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Application mapping of mesh based-NoC using multi-objective genetic algorithm
International Journal of Computers and Applications
Modelling and evaluation of a network on chip architecture using SDL
SDL'03 Proceedings of the 11th international conference on System design
THIN: a new hierarchical interconnection network-on-chip for SOC
ICA3PP'07 Proceedings of the 7th international conference on Algorithms and architectures for parallel processing
Simulation of a signal arbitration algorithm for a sensor array
EUROCAST'07 Proceedings of the 11th international conference on Computer aided systems theory
A low-overhead and reliable switch architecture for Network-on-Chips
Integration, the VLSI Journal
International Journal of High Performance Systems Architecture
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
International Journal of High Performance Systems Architecture
Efficient mapping of an image processing application for a network-on-chip based implementation
International Journal of High Performance Systems Architecture
Communication-aware task assignment algorithm for MPSoC using shared memory
Journal of Systems Architecture: the EUROMICRO Journal
PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design
Journal of Signal Processing Systems
Complement routing: A methodology to design reliable routing algorithm for Network on Chips
Microprocessors & Microsystems
Microprocessors & Microsystems
Scalable hardware support for conditional parallelization
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
A methodology for design of unbuffered router microarchitecture for S-mesh NoC
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Journal of Systems Architecture: the EUROMICRO Journal
A unified design space simulation environment for network-on-chip: fuse-N
International Journal of High Performance Systems Architecture
System design of full HD MVC decoding on mesh-based multicore NoCs
Microprocessors & Microsystems
A NoC-based hybrid message-passing/shared-memory approach to CMP design
Microprocessors & Microsystems
Performance comparison of some shared memory organizations for 2D mesh-like NOCs
Microprocessors & Microsystems
Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study
Microprocessors & Microsystems
On chip interconnects for multiprocessor turbo decoding architectures
Microprocessors & Microsystems
On the design and analysis of fault tolerant NoC architecture using spare routers
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Microprocessors & Microsystems
An analytical model for Network-on-Chip with finite input buffer
Frontiers of Computer Science in China
Reconfigurable multiprocessor systems: a review
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
Modified bundled-data as a new protocol for NoC asynchronous links
Microelectronics Journal
3D floorplanning of low-power and area-efficient Network-on-Chip architecture
Microprocessors & Microsystems
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Performance evaluation of a wormhole-routed algorithm for irregular mesh NoC interconnect
ICDCN'10 Proceedings of the 11th international conference on Distributed computing and networking
Expert Systems with Applications: An International Journal
Asynchronous switching for low-power networks-on-chip
Microelectronics Journal
A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips
Microprocessors & Microsystems
Throughput aware mapping for network on chip design of h.264 decoder
ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
GigaNetIC – a scalable embedded on-chip multiprocessor architecture for network applications
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Network on chip for parallel DSP architectures
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Efficient switches for network-on-chip based embedded systems
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Hierarchical graph: a new cost effective architecture for network on chip
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Network-on-Chip routing algorithms by breaking cycles
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A NoC system generator for the Sea-of-Cores era
Proceedings of the 8th FPGAWorld Conference
DTBR: A dynamic thermal-balance routing algorithm for Network-on-Chip
Computers and Electrical Engineering
A fault tolerant approach to object oriented design and synthesis of embedded systems
LADC'05 Proceedings of the Second Latin-American conference on Dependable Computing
The optimum network on chip architectures for video object plane decoder design
ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications
Intelligent on/off dynamic link management for on-chip networks
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router
Microprocessors & Microsystems
Formal verification methodology considerations for network on chips
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
An accurate performance model for network-on-chip and multicomputer interconnection networks
Journal of Parallel and Distributed Computing
A multi-objective mapping strategy for application specific emesh network-on-chip (noc)
ICSI'12 Proceedings of the Third international conference on Advances in Swarm Intelligence - Volume Part I
An QoS aware mapping of cores onto NoC architectures
ISPA'07 Proceedings of the 5th international conference on Parallel and Distributed Processing and Applications
A survey on application mapping strategies for Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
An energy-aware online task mapping algorithm in NoC-based system
The Journal of Supercomputing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power and Latency Optimized Deadlock-Free Routing Algorithm on Irregular 2D Mesh NoC using LBDRe
International Journal of Embedded and Real-Time Communication Systems
An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture
Wireless Personal Communications: An International Journal
Energy and buffer aware application mapping for networks-on-chip with self similar traffic
Journal of Systems Architecture: the EUROMICRO Journal
X-Network: An area-efficient and high-performance on-chip wormhole interconnect network
Microprocessors & Microsystems
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We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m x n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of switches and resources providing physical- architectural level design integration. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, an FPGA, a custom hardware block or any other intellectual property (IP) block, which fits into the available slot and complies with the interface of the NOC. The NOC architecture essentially is the on-chip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack. We define the concept of a region, which occupies an area of any number of resources and switches. This concept allows the NOC to accommodate large resources such as large memory banks, FPGA areas, or special purpose computation resources such as high performance multi-processors. The NOC design methodology consists of two phases. In the first phase a concrete architecture is derived from the general NOC template. The concrete architecture defines the number of switches and shape of the network, the kind and shape of regions and the number and kind of resources. The second phase maps the application onto the concrete architecture to form a concrete product.