A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Application-Specific System-on-a-Chip Multiprocessors
IEEE Design & Test
Gemini: An Optical Interconnection Network for Parallel Processing
IEEE Transactions on Parallel and Distributed Systems
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
On-chip networks: A scalable, communication-centric embedded system design paradigm
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Packet Routing in Dynamically Changing Networks on Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Automatic network generation for system-on-chip communication design
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Overview of the MPSoC design challenge
Proceedings of the 43rd annual Design Automation Conference
A design methodology for application-specific networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
Approaching Ideal NoC Latency with Pre-Configured Routes
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Reducing Interconnect Cost in NoC through Serialized Asynchronous Links
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
System level assessment of an optical NoC in an MPSoC platform
Proceedings of the conference on Design, automation and test in Europe
Photonic NoC for DMA Communications in Chip Multiprocessors
HOTI '07 Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
XY-turn model for deadlock free routing in honeycomb networks-on-chip
APCC'09 Proceedings of the 15th Asia-Pacific conference on Communications
Accelerating lightpath setup via broadcasting in binary-tree waveguide in optical NoCs
Proceedings of the Conference on Design, Automation and Test in Europe
A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Enabling quality-of-service in nanophotonic network-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Modeling and analysis of micro-ring based silicon photonic interconnect for embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
| Hi-index | 0.00 |
The performance of system-on-chip is determined not only by the performance of its functional units, but also by how efficiently they cooperate with one another. It is the on-chip communication architecture which determines the cooperation efficiency. Network-on-Chip (NoC) is introduced to improve communication bandwidth and power efficiency. However, traditional metallic interconnects consume significant amount of power to deliver large communication bandwidths. Optical NoCs are based on silicon optical interconnects with significant bandwidth and power advantages. Optical routers are the key enabling components of optical NoCs. This paper proposed a novel optical router architecture, ODOR, for optical NoCs based on XY routing algorithm. We compared ODOR with four other router architectures, and analyzed three aspects in details, including power consumption, optical power insertion loss, and the number of microresonators. The results show that ODOR has the lowest power consumption and losses and requires the least microresonators. ODOR has 40% less power consumption, 40% less loss, and 52% less microresonator than the full-connected crossbar. Furthermore, ODOR has a special feature which guarantees the maximum power to route a packet through a network to be a small constant number, regardless of the network size. The maximum power consumption is 0.96fJ/bit under current technology. We simulated a 6x6 2D mesh NoC based on ODOR, and showed the end-to-end delay and network throughput under different offered loads and packet sizes.