The network architecture of the Connection Machine CM-5 (extended abstract)
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
A multicast inter-task communication protocol for embedded multiprocessor systems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
A design methodology for application-specific networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
A collision model for randomized routing in fat-tree networks
Journal of Parallel and Distributed Computing
Predictions of CMOS compatible on-chip optical interconnect
Integration, the VLSI Journal
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Proceedings of the 34th annual international symposium on Computer architecture
System level assessment of an optical NoC in an MPSoC platform
Proceedings of the conference on Design, automation and test in Europe
The case for low-power photonic networks on chip
Proceedings of the 44th annual Design Automation Conference
Photonic NoC for DMA Communications in Chip Multiprocessors
HOTI '07 Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
UNION: a unified inter/intra-chip optical network for chip multiprocessors
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Crosstalk noise and bit error rate analysis for optical network-on-chip
Proceedings of the 47th Design Automation Conference
Accelerating lightpath setup via broadcasting in binary-tree waveguide in optical NoCs
Proceedings of the Conference on Design, Automation and Test in Europe
All-optical wavelength-routed noc based on a novel hierarchical topology
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Scalable architecture for a contention-free optical network on-chip
Journal of Parallel and Distributed Computing
Proceedings of the Fifth International Workshop on Network on Chip Architectures
Reduction methods for adapting optical network on chip topologies to 3D architectures
Microprocessors & Microsystems
Packet switching optical network-on-chip architectures
Computers and Electrical Engineering
System-level modeling and analysis of thermal effects in optical networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PROTON: an automatic place-and-route tool for optical networks-on-chip
Proceedings of the International Conference on Computer-Aided Design
Journal of Systems Architecture: the EUROMICRO Journal
Towards a scalable, low-power all-optical architecture for networks-on-chip
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
| Hi-index | 0.00 |
Multiprocessor system-on-chip (MPSoC) is an attractive platform for high-performance applications. Networks-on-Chip (NoCs) can improve the on-chip communication bandwidth of MPSoCs. However, traditional metallic interconnects consume significant amount of power to deliver even higher communication bandwidth required in the near future. Optical NoCs are based on CMOS-compatible optical waveguides and microresonators, and promise significant bandwidth and power advantages. This paper proposes a fat tree-based optical NoC (FONoC) including its topology, floorplan, protocols, and a low-power and low-cost optical router, optical turnaround router (OTAR). Different from other optical NoCs, FONoC does not require building a separate electronic NoC for network control. It carries both payload data and network control data on the same optical network, while using circuit switching for the former and packet switching for the latter. The FONoC protocols are designed to minimize network control data and the related power consumption. An optimized turnaround routing algorithm is designed to utilize the low-power feature of OTAR, which can passively route packets without powering on any microresonator in 40% of all cases. Comparing with other optical routers, OTAR has the lowest optical power loss and uses the lowest number of microresonators. An analytical model is developed to characterize the power consumption of FONoC. We compare the power consumption of FONoC with a matched electronic NoC in 45 nm, and show that FONoC can save 87% power comparing with the electronic NoC on a 64-core MPSoC. We simulate the FONoC for the 64-core MPSoC and show the end-to-end delay and network throughput under different offered loads and packet sizes.