A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
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Route packets, not wires: on-chip inteconnection networks
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Traffic analysis for on-chip networks design of multimedia applications
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Self-Similar Network Traffic and Performance Evaluation
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Interconnection Networks: An Engineering Approach
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A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers
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A Network on Chip Architecture and Design Methodology
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A simplified executable model to evaluate latency and throughput of networks-on-chip
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Routability of network topologies in FPGAs
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Embedding Intelligence into EDA Tools
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Evaluating SoC Network Performance in MPEG-4 Encoder
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Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Evaluating the energy consumption and the silicon area of on-chip interconnect architectures
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Region-based routing: a mechanism to support efficient routing algorithms in NoCs
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Hybrid wireless Network on Chip: a new paradigm in multi-core design
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Wire cost and communication analysis of self-assembled interconnect models for Networks-on-Chip
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A networks-on-chip architecture design space exploration - The LIB
Computers and Electrical Engineering
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
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On hamming product codes with type-II hybrid ARQ for on-chip interconnects
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A DAMQ shared buffer scheme for network-on-chip
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A new performance measure for characterizing fault rings in interconnection networks
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An analytical performance model for the Spidergon NoC with virtual channels
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A cost-effective load-balancing policy for tile-based, massive multi-core packet processors
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Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
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Reconfigurable Networks on Chip: DRNoC architecture
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| Hi-index | 14.98 |
Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.