Toward achieving energy efficiency in presence of deep submicron noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Energy characterization of a tiled architecture processor with on-chip networks
Proceedings of the 2003 international symposium on Low power electronics and design
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Error Control Coding, Second Edition
Error Control Coding, Second Edition
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Thermal Impacts on NoC Interconnects
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
Proceedings of the conference on Design, automation and test in Europe
Configurable Error Control Scheme for NoC Signal Integrity
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Journal of Electronic Testing: Theory and Applications
Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Analysis of forward error correction methods for nanoscale networks-on-chip
Proceedings of the 2nd international conference on Nano-Networks
Power consumption of fault tolerant busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SSMCB: low-power variation-tolerant source-synchronous multicycle bus
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Extended Hamming product codes analytical performance evaluation for low error rate applications
IEEE Transactions on Wireless Communications
Error control schemes for on-chip communication links: the energy-reliability tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Exploiting parity computation latency for on-chip crosstalk reduction
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Resilient microring resonator based photonic networks
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Self-calibrated energy-efficient and reliable channels for on-chip interconnection networks
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Addressing network-on-chip router transient errors with inherent information redundancy
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
Dual-layer adaptive error control for network-on-chip links
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
International Journal of Computer Applications in Technology
| Hi-index | 0.00 |
We present hardware performance analyses of Hamming product codes combined with type-II hybrid automatic repeat request (HARQ), for on-chip interconnects. Input flit width and the number of rows in the product code message are investigated for their impact on the number of wires in the link, codec delay, reliability, and energy consumption. Analytical models are presented to estimate codec delay and residual flit error rate. The analyses are validated by comparison with simulation results. In a case study using H.264 video encoder in a network-on-chip environment, the method of combining Hamming product codes with type-II HARQ achieves several orders of magnitude improvement in residual flit error rate. For a given residual flit error rate requirement (e.g., 10-20), this method yields up to 50% energy improvement over other error control methods in high-noise conditions.