Asynchronous transient resilient links for NoC
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
On hamming product codes with type-II hybrid ARQ for on-chip interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A flexible parallel simulator for networks-on-chip with error control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Self-adaptive system for addressing permanent errors in on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Error resilience of intra-die and inter-die communication with 3D Spidergon STNoC
Proceedings of the Conference on Design, Automation and Test in Europe
Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-layer adaptive error control for network-on-chip links
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes
Microprocessors & Microsystems
International Journal of Computer Applications in Technology
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In this paper we propose a novel error control scheme to cope with errors affecting the communication links of a NoC. Our scheme can be configured in Correction Mode, Detection Mode, and Mixed Mode, depending on the particular application, thus allowing to meet different Quality of Service (QoS) levels in terms of error control. For each configuration mode, we propose different error control policies and we consider SEC Hamming codes, SEC/DED Hsiao codes, and Symbol Error Correcting codes. We evaluate advantages and drawbacks of each approach, in terms of signal integrity, area overhead and impact on performance.