A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Error-correction and crosstalk avoidance in DSM busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New ECC for Crosstalk Impact Minimization
IEEE Design & Test
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
Proceedings of the conference on Design, automation and test in Europe
Configurable Error Control Scheme for NoC Signal Integrity
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Journal of Electronic Testing: Theory and Applications
Exploiting ECC Redundancy to Minimize Crosstalk Impact
IEEE Design & Test
Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
On hamming product codes with type-II hybrid ARQ for on-chip interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects
DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multi-level design methodology of multistage interconnection network for MPSOCs
International Journal of Computer Applications in Technology
Self-calibrated energy-efficient and reliable channels for on-chip interconnection networks
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Error control schemes for on-chip communication links: the energy-reliability tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With the shrinking geometry, interconnection wires in network-on-chip NoC will be exposed to different noise sources such as crosstalk coupling and supply voltage fluctuation that cause random and burst errors. These errors affect the reliability of NoC. Hence error control codes are incorporated to make the NoC robust against errors. In this paper, we propose a novel low complex error control code to correct random and burst errors and simultaneously avoid crosstalk. The proposed error control code uses a novel triplicate add parity TAP scheme to avoid crosstalk in the interconnection links. The proposed error control code can detect burst errors of three and correct random or burst errors up to two. Hybrid automatic repeat request HARQ system is employed when burst errors of three occurs. The proposed error control code outperforms the existing error control code in terms of residual flit error rate and energy consumption.