A Simulation Study of the CRAY X-MP Memory System
IEEE Transactions on Computers
A Unified theory of interconnection network structure
Theoretical Computer Science
The SP2 high-performance switch
IBM Systems Journal
Survey of ATM switch architectures
Computer Networks and ISDN Systems
A quantitive comparision of iterative scheduling algoithm for input-queued switches
Computer Networks and ISDN Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
The future of multiprocessor systems-on-chips
Proceedings of the 41st annual Design Automation Conference
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Floorplan-aware automated synthesis of bus-based communication architectures
Proceedings of the 42nd annual Design Automation Conference
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices
IEEE Design & Test
A dynamically reconfigurable packet-switched network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A practical FPGA-based framework for novel CMP research
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Towards a formal theory of on chip communications in the ACL2 logic
ACL2 '06 Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications
Proceedings of the conference on Design, automation and test in Europe
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
The Performance of Multistage Interconnection Networks for Multiprocessors
IEEE Transactions on Computers
Executable formal specification and validation of NoC communication infrastructures
Proceedings of the 21st annual symposium on Integrated circuits and system design
A formal approach to the verification of networks on chip
EURASIP Journal on Embedded Systems
Verification of AMBA Using a Combination of Model Checking and Theorem Proving
Electronic Notes in Theoretical Computer Science (ENTCS)
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Research on half-mesh topology based on binary model and HTF-XY routing algorithm
International Journal of Computer Applications in Technology
Social ant colony-inspired modelling approach for rapid response design
International Journal of Computer Applications in Technology
New heuristic algorithms for low-energy mapping and routing in 3D NoC
International Journal of Computer Applications in Technology
Auto-design systematic methodology of cluster MPSoC for multiple concurrent applications
International Journal of Computer Applications in Technology
International Journal of Computer Applications in Technology
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In this paper, we propose a design methodology of Multistage Interconnection Networks (MINs) for multiprocessor system on chip. The framework covers the design step from algorithm level to RTL. We first develop a functional formalisation of MIN-based on-chip network at a high level of abstraction. The specification and the validation of the model have been defined in the logic of ACL2 proving system. The main objective in this step is to provide a formal description of the network that integrates architectural parameters, which have a huge impact on design costs. After validating the functional model, step 2 consists in the design and the implementation of the Delta multistage NoC dedicated to multiprocessor architectures on reconfigurable platforms FPGA. In the last step, we propose an evaluation methodology based on performance and cost metrics to evaluate different topologies of dynamic network through applications with different numbers of cores. We also show in the proposed framework that MIN will become future general-purpose communication architecture for MPSOCs.