Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
IEEE Transactions on Parallel and Distributed Systems
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
Proceedings of the 32nd annual international symposium on Computer Architecture
Replacing global wires with an on-chip network: a power analysis
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Time and energy efficient mapping of embedded applications onto NoCs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Proceedings of the 33rd annual international symposium on Computer Architecture
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
Proceedings of the 2nd international conference on Nano-Networks
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
IEEE Transactions on Computers
Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs
Journal of Systems Architecture: the EUROMICRO Journal
Sunfloor 3D: a tool for networks on chip topology synthesis for 3-D systems on chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application-specific temperature reduction systematic methodology for 2d and 3d networks-on-chip
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A multi-level design methodology of multistage interconnection network for MPSOCs
International Journal of Computer Applications in Technology
High performance power flow algorithm for symmetrical distribution networks with unbalanced loading
International Journal of Computer Applications in Technology
A Layer-Multiplexed 3D On-Chip Network Architecture
IEEE Embedded Systems Letters
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ORION 2.0: A Power-Area Simulator for Interconnection Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cooperative game-based routing approach for wireless sensor network
International Journal of Computer Applications in Technology
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Three Dimensional Network on Chip 3D NoC, which reduces the average number of hops traversed by a packet, can achieve better performance than the traditional 2D NoC. However, when routers deliver packets in 3D NoC, more energy consumption is needed. High-energy consumption and small packaging density will cause excessive heat, which increases vulnerability of the system in performance and reliability. In this paper, we present a low-energy consumption mapping algorithm based on the symmetry of the architecture and construct a deadlock-free routing algorithm using mapping result information. Our proposed algorithms can reduce the total energy consumption of communication and achieve a good system performance under the bandwidth constraints. To evaluate the efficacy of the algorithms, we perform experiments on several benchmarks and compare the proposed algorithms with other existing algorithms. Experimental results show that, for complex benchmarks, our proposed algorithms get better results than others.