ORION 2.0: A Power-Area Simulator for Interconnection Networks

Authors:
Andrew B. Kahng;Bin Li;Li-Shiuan Peh;Kambiz Samadi
Affiliations:
Departments of Computer Science and Engineering, and of Electrical and Computer Engineering, University of California at San Diego, La Jolla,;Intel Corporation, Hillsboro,;Department of Electrical Engineering and Computer Science, MIT, Cambridge,;Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla,
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

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Abstract

As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. In this work, we present ORION 2.0, an enhanced NoC power and area simulator, which offers significant accuracy improvement relative to its predecessor, ORION 1.0.