Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Proceedings of the 6th international workshop on Hardware/software codesign
Noise considerations in circuit optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI
Analog Integrated Circuits and Signal Processing
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
Proceedings of the conference on Design, automation and test in Europe
Power Supply Noise in SoCs: Metrics, Management, and Measurement
IEEE Design & Test
Power grid analysis benchmarks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Energy and reliability oriented mapping for regular Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Transition density: a new measure of activity in digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ORION 2.0: A Power-Area Simulator for Interconnection Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Surface wave communication system for on-chip and off-chip interconnects
Proceedings of the Fifth International Workshop on Network on Chip Architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
Power supply integrity has become a critical concern with the rapid shrinking of device dimensions and the ever increasing power consumption in nano-scale integration. Particularly, power supply noise is strongly correlated to the spatial distribution of activity densities and this can be attributed to the on-chip communication, which dictates the power dissipation and overall system performance in networks-on-chip. In this paper, we propose a new mapping strategy aiming to create a balanced activity distribution across the whole chip. We formulate the problem of application mapping as a minimization of the activity density by employing a repulsive force-based objective function. Metrics of regional activity density and characteristics of its impact on power supply noise are considered. The proposed method has been rigorously evaluated based on a large set of real-application benchmarks. Significant reduction in power supply noise can be achieved with negligible energy overhead. This new approach would provide a more scalable solution for future large-scale system integration.